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Thu, 12 Mar 2026 04:42:22 -0700 (PDT) Received: from sifive.com ([136.226.240.165]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2aeae246ff0sm80015205ad.27.2026.03.12.04.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 04:42:21 -0700 (PDT) Date: Thu, 12 Mar 2026 19:42:18 +0800 From: Max Chou To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags Message-ID: References: <20260306071105.3328365-1-max.chou@sifive.com> <20260306071105.3328365-6-max.chou@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=max.chou@sifive.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026-03-09 15:01, Alistair Francis wrote: > On Fri, Mar 6, 2026 at 5:13 PM Max Chou wrote: > > > > We have more than 32-bits worth of state per TB, so use the > > tb->cs_base, which is otherwise unused for RISC-V, as the extend flag. > > > > Reviewed-by: Daniel Henrique Barboza > > Reviewed-by: Chao Liu > > Signed-off-by: Max Chou > > --- > > include/exec/translation-block.h | 1 + > > target/riscv/cpu.h | 3 +++ > > target/riscv/tcg/tcg-cpu.c | 7 ++++++- > > 3 files changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h > > index 4f83d5bec9..40cc699031 100644 > > --- a/include/exec/translation-block.h > > +++ b/include/exec/translation-block.h > > @@ -65,6 +65,7 @@ struct TranslationBlock { > > * arm: an extension of tb->flags, > > * s390x: instruction data for EXECUTE, > > * sparc: the next pc of the instruction queue (for delay slots). > > + * riscv: an extension of tb->flags, > > */ > > uint64_t cs_base; > > > Hi Alistair, I’m curious to know if you mean adding more details here, such as specifying the bit width for misa (e.g., 32 bits) or the bit width for ALTFMT (e.g., 1 bit). If so, I’ll include these details in the v6 version. Thanks, rnax > We need to update the comment in `struct TranslationBlock` for > `target_ulong cs_base` > > Alistair >