diff for duplicates of <abcae019e6ae749b17ecb0c721fd3177@mailhost.ics.forth.gr>

diff --git a/a/1.txt b/N1/1.txt
index fd025e6..860fb13 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,8 +1,8 @@
-???? 2018-11-06 18:20, Mark Rutland ??????:
+Στις 2018-11-06 18:20, Mark Rutland έγραψε:
 > On Tue, Nov 06, 2018 at 05:26:01PM +0200, Nick Kossifidis wrote:
->> ???? 2018-11-06 16:13, Sudeep Holla ??????:
+>> Στις 2018-11-06 16:13, Sudeep Holla έγραψε:
 >> > On Fri, Nov 02, 2018 at 08:58:39PM +0200, Nick Kossifidis wrote:
->> > > ???? 2018-11-02 01:04, Atish Patra ??????:
+>> > > Στις 2018-11-02 01:04, Atish Patra έγραψε:
 >> > > > This patch series adds the cpu topology for RISC-V. It contains
 >> > > > both the DT binding and actual source code. It has been tested on
 >> > > > QEMU & Unleashed board.
@@ -167,16 +167,16 @@ we find them / not find them at all). All I'm saying is that I prefer
 this:
 
 cpus {
-  cpu at 0 {
+  cpu@0 {
    ...
   };
-  cpu at 1 {
+  cpu@1 {
    ...
   };
-  cpu at 2 {
+  cpu@2 {
    ...
   };
-  cpu at 3 {
+  cpu@3 {
    ...
   };
 };
@@ -209,28 +209,28 @@ cluster0 {
 over this:
 
 cpus {
-  cpu at 0 {
+  cpu@0 {
    ...
    power-domains = <&pdc 0>;
    capacity-dmips-mhz = <578>;
    numa-node-id = <0>;
    ...
   };
-  cpu at 1 {
+  cpu@1 {
    ...
    power-domains = <&pdc 0>;
    capacity-dmips-mhz = <578>;
    numa-node-id = <0>;
    ...
   };
-  cpu at 2 {
+  cpu@2 {
    ...
    power-domains = <&pdc 1>;
    capacity-dmips-mhz = <1024>;
    numa-node-id = <1>;
    ...
   };
-  cpu at 3 {
+  cpu@3 {
    ...
    power-domains = <&pdc 2>;
    capacity-dmips-mhz = <1024>;
@@ -266,22 +266,22 @@ standard I think). The below comes from HiFive unleashed's device tree
 (U540Config.dts) that follows the spec:
 
 cpus {
-  cpu at 1 {
+  cpu@1 {
    ...
    next-level-cache = <&L24 &L0>;
    ...
   };
-  cpu at 2 {
+  cpu@2 {
    ...
    next-level-cache = <&L24 &L0>;
    ...
   };
-  cpu at 3 {
+  cpu@3 {
    ...
    next-level-cache = <&L24 &L0>;
    ...
   };
-  cpu at 4 {
+  cpu@4 {
    ...
    next-level-cache = <&L24 &L0>;
    ...
@@ -289,7 +289,7 @@ cpus {
 };
 
 L2: soc {
-  L0: cache-controller at 2010000 {
+  L0: cache-controller@2010000 {
    cache-block-size = <64>;
    cache-level = <2>;
    cache-sets = <2048>;
@@ -312,7 +312,7 @@ be better ?
 
 cluster0 {
   core0 {
-   cache-controller at 2010000 {
+   cache-controller@2010000 {
     cache-block-size = <64>;
     cache-level = <2>;
     cache-sets = <2048>;
@@ -344,7 +344,7 @@ it
 like this instead:
 
 cluster0 {
-  cache-controller at 2010000 {
+  cache-controller@2010000 {
    cache-block-size = <64>;
    cache-level = <2>;
    cache-sets = <2048>;
@@ -399,7 +399,7 @@ cluster0 {
 and in the second example:
 
 cluster0 {
-  cache-controller at 2010000 {
+  cache-controller@2010000 {
    cache-block-size = <64>;
    cache-level = <2>;
    cache-sets = <2048>;
@@ -416,3 +416,8 @@ Thank you for your time !
 
 Regards,
 Nick
+
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index f5f3b5e..027094e 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -3,17 +3,31 @@
  "ref\020181106141331.GA28458@e107155-lin\0"
  "ref\0969fc2a5198984e0dfe8c3f585dc65f9@mailhost.ics.forth.gr\0"
  "ref\020181106162051.w7fyweuxrl7ujzuz@lakrids.cambridge.arm.com\0"
- "From\0mick@ics.forth.gr (Nick Kossifidis)\0"
- "Subject\0[RFC 0/2] Add RISC-V cpu topology\0"
+ "From\0Nick Kossifidis <mick@ics.forth.gr>\0"
+ "Subject\0Re: [RFC 0/2] Add RISC-V cpu topology\0"
  "Date\0Wed, 07 Nov 2018 04:31:34 +0200\0"
- "To\0linux-riscv@lists.infradead.org\0"
+ "To\0Mark Rutland <mark.rutland@arm.com>"
+ " Sudeep Holla <sudeep.holla@arm.com>\0"
+ "Cc\0devicetree@vger.kernel.org"
+  Damien.LeMoal@wdc.com
+  alankao@andestech.com
+  hch@infradead.org
+  anup@brainfault.org
+  palmer@sifive.com
+  linux-kernel@vger.kernel.org
+  zong@andestech.com
+  Atish Patra <atish.patra@wdc.com>
+  robh+dt@kernel.org
+  Nick Kossifidis <mick@ics.forth.gr>
+  linux-riscv@lists.infradead.org
+ " tglx@linutronix.de\0"
  "\00:1\0"
  "b\0"
- "???? 2018-11-06 18:20, Mark Rutland ??????:\n"
+ "\316\243\317\204\316\271\317\202 2018-11-06 18:20, Mark Rutland \316\255\316\263\317\201\316\261\317\210\316\265:\n"
  "> On Tue, Nov 06, 2018 at 05:26:01PM +0200, Nick Kossifidis wrote:\n"
- ">> ???? 2018-11-06 16:13, Sudeep Holla ??????:\n"
+ ">> \316\243\317\204\316\271\317\202 2018-11-06 16:13, Sudeep Holla \316\255\316\263\317\201\316\261\317\210\316\265:\n"
  ">> > On Fri, Nov 02, 2018 at 08:58:39PM +0200, Nick Kossifidis wrote:\n"
- ">> > > ???? 2018-11-02 01:04, Atish Patra ??????:\n"
+ ">> > > \316\243\317\204\316\271\317\202 2018-11-02 01:04, Atish Patra \316\255\316\263\317\201\316\261\317\210\316\265:\n"
  ">> > > > This patch series adds the cpu topology for RISC-V. It contains\n"
  ">> > > > both the DT binding and actual source code. It has been tested on\n"
  ">> > > > QEMU & Unleashed board.\n"
@@ -178,16 +192,16 @@
  "this:\n"
  "\n"
  "cpus {\n"
- "  cpu at 0 {\n"
+ "  cpu@0 {\n"
  "   ...\n"
  "  };\n"
- "  cpu at 1 {\n"
+ "  cpu@1 {\n"
  "   ...\n"
  "  };\n"
- "  cpu at 2 {\n"
+ "  cpu@2 {\n"
  "   ...\n"
  "  };\n"
- "  cpu at 3 {\n"
+ "  cpu@3 {\n"
  "   ...\n"
  "  };\n"
  "};\n"
@@ -220,28 +234,28 @@
  "over this:\n"
  "\n"
  "cpus {\n"
- "  cpu at 0 {\n"
+ "  cpu@0 {\n"
  "   ...\n"
  "   power-domains = <&pdc 0>;\n"
  "   capacity-dmips-mhz = <578>;\n"
  "   numa-node-id = <0>;\n"
  "   ...\n"
  "  };\n"
- "  cpu at 1 {\n"
+ "  cpu@1 {\n"
  "   ...\n"
  "   power-domains = <&pdc 0>;\n"
  "   capacity-dmips-mhz = <578>;\n"
  "   numa-node-id = <0>;\n"
  "   ...\n"
  "  };\n"
- "  cpu at 2 {\n"
+ "  cpu@2 {\n"
  "   ...\n"
  "   power-domains = <&pdc 1>;\n"
  "   capacity-dmips-mhz = <1024>;\n"
  "   numa-node-id = <1>;\n"
  "   ...\n"
  "  };\n"
- "  cpu at 3 {\n"
+ "  cpu@3 {\n"
  "   ...\n"
  "   power-domains = <&pdc 2>;\n"
  "   capacity-dmips-mhz = <1024>;\n"
@@ -277,22 +291,22 @@
  "(U540Config.dts) that follows the spec:\n"
  "\n"
  "cpus {\n"
- "  cpu at 1 {\n"
+ "  cpu@1 {\n"
  "   ...\n"
  "   next-level-cache = <&L24 &L0>;\n"
  "   ...\n"
  "  };\n"
- "  cpu at 2 {\n"
+ "  cpu@2 {\n"
  "   ...\n"
  "   next-level-cache = <&L24 &L0>;\n"
  "   ...\n"
  "  };\n"
- "  cpu at 3 {\n"
+ "  cpu@3 {\n"
  "   ...\n"
  "   next-level-cache = <&L24 &L0>;\n"
  "   ...\n"
  "  };\n"
- "  cpu at 4 {\n"
+ "  cpu@4 {\n"
  "   ...\n"
  "   next-level-cache = <&L24 &L0>;\n"
  "   ...\n"
@@ -300,7 +314,7 @@
  "};\n"
  "\n"
  "L2: soc {\n"
- "  L0: cache-controller at 2010000 {\n"
+ "  L0: cache-controller@2010000 {\n"
  "   cache-block-size = <64>;\n"
  "   cache-level = <2>;\n"
  "   cache-sets = <2048>;\n"
@@ -323,7 +337,7 @@
  "\n"
  "cluster0 {\n"
  "  core0 {\n"
- "   cache-controller at 2010000 {\n"
+ "   cache-controller@2010000 {\n"
  "    cache-block-size = <64>;\n"
  "    cache-level = <2>;\n"
  "    cache-sets = <2048>;\n"
@@ -355,7 +369,7 @@
  "like this instead:\n"
  "\n"
  "cluster0 {\n"
- "  cache-controller at 2010000 {\n"
+ "  cache-controller@2010000 {\n"
  "   cache-block-size = <64>;\n"
  "   cache-level = <2>;\n"
  "   cache-sets = <2048>;\n"
@@ -410,7 +424,7 @@
  "and in the second example:\n"
  "\n"
  "cluster0 {\n"
- "  cache-controller at 2010000 {\n"
+ "  cache-controller@2010000 {\n"
  "   cache-block-size = <64>;\n"
  "   cache-level = <2>;\n"
  "   cache-sets = <2048>;\n"
@@ -426,6 +440,11 @@
  "Thank you for your time !\n"
  "\n"
  "Regards,\n"
- Nick
+ "Nick\n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
-010313ed0feedfb3117bbfa75fa5989010a1ecb7997f0899a5235fa0c9792492
+7087b58a725e9ba1704301f55b0a3a34f18c00082435d051bec489718fd27bc2
