From: Raag Jadav <raag.jadav@intel.com>
To: "Tauro, Riana" <riana.tauro@intel.com>
Cc: intel-xe@lists.freedesktop.org, matthew.brost@intel.com,
rodrigo.vivi@intel.com, michal.wajdeczko@intel.com,
matthew.d.roper@intel.com, umesh.nerlige.ramappa@intel.com,
mallesh.koujalagi@intel.com, soham.purkait@intel.com,
anoop.c.vijay@intel.com, aravind.iddamsetty@linux.intel.com
Subject: Re: [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support
Date: Mon, 23 Mar 2026 12:40:08 +0100 [thread overview]
Message-ID: <acEmmG9VgdidyP4z@black.igk.intel.com> (raw)
In-Reply-To: <c05cf845-311a-440e-973b-7bc17359fecb@intel.com>
On Thu, Mar 19, 2026 at 07:39:12PM +0530, Tauro, Riana wrote:
> On 3/12/2026 2:36 PM, Raag Jadav wrote:
> > System controller reports different types of events to GFX endpoint for
> > different usecases, add initial support for them. This will be further
> > extended to service those usecases.
> >
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> > v2: Handle unexpected response length (Mallesh)
> > v3: Handle event flood (Mallesh)
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl.c | 4 +
> > drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl_event.c | 82 +++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 +++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> > 6 files changed, 150 insertions(+)
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> > create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 543eb0b2430b..373adb20afb2 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -125,6 +125,7 @@ xe-y += xe_bb.o \
> > xe_survivability_mode.o \
> > xe_sync.o \
> > xe_sysctrl.o \
> > + xe_sysctrl_event.o \
> > xe_sysctrl_mailbox.o \
> > xe_tile.o \
> > xe_tile_sysfs.o \
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 30349df1c04b..63b9aaf98669 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -42,6 +42,10 @@ static void sysctrl_fini(void *arg)
> > static void xe_sysctrl_work(struct work_struct *work)
> > {
> > + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> > +
> > + guard(mutex)(&sc->work_lock);
> > + xe_sysctrl_event(sc);
> > }
> > /**
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index ff60d42b52a7..0821ea44893d 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -18,5 +18,6 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> > int xe_sysctrl_init(struct xe_device *xe);
> > void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > +void xe_sysctrl_event(struct xe_sysctrl *sc);
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > new file mode 100644
> > index 000000000000..47afca586bd1
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -0,0 +1,82 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_device.h"
> > +#include "xe_irq.h"
> > +#include "xe_printk.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_event_types.h"
> > +#include "xe_sysctrl_mailbox.h"
> > +#include "xe_sysctrl_mailbox_types.h"
> > +
> > +static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> > + struct xe_sysctrl_mailbox_command *command)
> > +{
> > + struct xe_sysctrl_event_response response;
> > + struct xe_device *xe = sc_to_xe(sc);
> > + u32 count = 0;
> > + size_t len;
> > + int ret;
> > +
> > + command->data_out = &response;
> > + command->data_out_len = sizeof(response);
> > +
> > + do {
> > + memset(&response, 0, sizeof(response));
> > +
> > + ret = xe_sysctrl_send_command(sc, command, &len);
> > + if (ret) {
> > + xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
> > + return;
> > + }
> > +
> > + if (len != sizeof(response)) {
> > + xe_err(xe, "sysctrl: unexpected pending event response length %ld\n", len);
> > + return;
> > + }
> > +
> > + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> > + xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > + } else {
> > + xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> > + return;
> > + }
> > +
> > + if (++count > XE_SYSCTRL_EVENT_FLOOD) {
> > + xe_err(xe, "sysctrl: event flooding\n");
> > + return;
> > + }
> > +
> > + xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
> > + } while (response.count);
> > +}
> > +
> > +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> > + struct xe_sysctrl_app_msg_hdr *header,
> > + struct xe_sysctrl_event_request *request)
> > +{
> > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > +
> > + header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> > + REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
> > +
> > + request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> > + request->fn = PCI_FUNC(pdev->devfn);
> > +}
> > +
> > +void xe_sysctrl_event(struct xe_sysctrl *sc)
> > +{
> > + struct xe_sysctrl_mailbox_command command = {};
> > + struct xe_sysctrl_event_request request = {};
> > + struct xe_sysctrl_app_msg_hdr header = {};
> > +
> > + xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
> > +
> > + command.header = header;
> > + command.data_in = &request;
> > + command.data_in_len = sizeof(request);
> > +
> > + xe_sysctrl_get_pending_event(sc, &command);
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > new file mode 100644
> > index 000000000000..1430a7ee2b39
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > @@ -0,0 +1,52 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> > +#define _XE_SYSCTRL_EVENT_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_SYSCTRL_EVENT_DATA_LEN 59
> > +
> > +/* Modify as needed */
> > +#define XE_SYSCTRL_EVENT_FLOOD 16
> > +
> > +enum xe_sysctrl_event {
> > + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
> > +};
> > +
> > +/**
> > + * struct xe_sysctrl_event_request - Request structure for pending event
> > + */
> > +struct xe_sysctrl_event_request {
> > + /** @vector: MSI-X vector that was triggered */
> > + u32 vector;
> > + /** @fn: Function index (0-7) of PCIe device */
> > + u8 fn;
> > + /** @reserved: Reserved for future use */
> > + u32 reserved:24;
> > + /** @reserved2: Reserved for future use */
> > + u32 reserved2[2];
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sysctrl_event_response - Response structure for pending event
> > + */
> > +struct xe_sysctrl_event_response {
> > + /** @count: Number of pending events */
> > + u32 count;
> > + /** @event: Pending event */
> > + enum xe_sysctrl_event event;
> > + /** @timestamp: Timestamp of most recent event */
> > + u64 timestamp;
> > + /** @extended: Event has extended payload */
> > + u8 extended:1;
> > + /** @reserved: Reserved for future use */
> > + u32 reserved:31;
> > + /** @data: Generic event data */
> > + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> > +} __packed;
>
> Let's add this in xe_ras_types.h to have a separate RAS layer that utilizes
> system controller.
>
> Since multiple functions will be using system controller keeping their
> headers and functions in a separate file
>
> will avoid cluttering everything in a single file. Let sysctrl.c only be an
> interface to the firmware.
I had an impression that a sysctrl event is meant for wider usecases than
RAS. Did things change (again)?
Raag
> > +
> > +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > index 91460be9e22c..d59a825597d3 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > @@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
> > #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> > FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> > +/* Command groups */
> > +enum xe_sysctrl_group {
> > + XE_SYSCTRL_GROUP_GFSP = 0x01,
> > +};
> > +
> > +/* Commands supported by GFSP group */
> > +enum xe_sysctrl_gfsp_cmd {
> > + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> > +};
> > +
> > void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> > int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> > struct xe_sysctrl_mailbox_command *cmd,
next prev parent reply other threads:[~2026-03-23 11:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-12 9:06 [PATCH v3 0/4] Introduce Xe Correctable Error Handling Raag Jadav
2026-03-12 9:06 ` [PATCH v3 1/4] drm/xe/sysctrl: Add System Controller Raag Jadav
2026-03-12 9:06 ` [PATCH v3 2/4] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
2026-03-17 5:47 ` Mallesh, Koujalagi
2026-03-23 11:32 ` Raag Jadav
2026-03-12 9:06 ` [PATCH v3 3/4] drm/xe/sysctrl: Add system controller event support Raag Jadav
2026-03-19 14:09 ` Tauro, Riana
2026-03-23 11:40 ` Raag Jadav [this message]
2026-03-23 12:27 ` Mallesh, Koujalagi
2026-03-24 4:42 ` Raag Jadav
2026-03-12 9:06 ` [PATCH v3 4/4] drm/xe/ras: Introduce correctable error handling Raag Jadav
2026-03-19 14:00 ` Tauro, Riana
2026-03-23 11:45 ` Raag Jadav
2026-03-23 14:46 ` Mallesh, Koujalagi
2026-03-24 4:43 ` Raag Jadav
2026-03-12 10:27 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev3) Patchwork
2026-03-12 10:28 ` ✓ CI.KUnit: success " Patchwork
2026-03-12 11:15 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-13 6:22 ` ✓ Xe.CI.FULL: " Patchwork
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