From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Luca Coelho <luciano.coelho@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
jani.nikula@linux.intel.com
Subject: Re: [PATCH 7/8] drm/i915/display: move pre-HSW clock gating init to display
Date: Tue, 24 Mar 2026 17:04:33 +0200 [thread overview]
Message-ID: <acKoAdGa3s1S5Pqm@intel.com> (raw)
In-Reply-To: <20260324143420.310800-8-luciano.coelho@intel.com>
On Tue, Mar 24, 2026 at 04:29:56PM +0200, Luca Coelho wrote:
> Move the remaining pre-HSW display clock gating programming into
> display.
>
> This also drops display register includes from intel_clock_gating.c.
>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
> .../i915/display/intel_display_clock_gating.c | 100 ++++++++++++++++
> .../i915/display/intel_display_clock_gating.h | 12 ++
> drivers/gpu/drm/i915/intel_clock_gating.c | 109 +-----------------
> 3 files changed, 118 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> index 0b2edf6acb79..5809c49dccf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -6,11 +6,13 @@
> #include <drm/intel/intel_gmd_misc_regs.h>
>
> #include "intel_de.h"
> +#include "i9xx_plane_regs.h"
> #include "intel_display.h"
> #include "intel_display_clock_gating.h"
> #include "intel_display_regs.h"
>
> #include "i915_drv.h"
> +#include "i915_reg.h"
>
> static void intel_display_gen9_init_clock_gating(struct intel_display *display,
> bool has_llc)
> @@ -156,3 +158,101 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
> intel_display_hsw_init_clock_gating_common(display,
> HSW_UNMASK_VBL_TO_REGS_IN_SRD);
> }
> +
> +void intel_display_disable_trickle_feed(struct intel_display *display)
> +{
> + enum pipe pipe;
> +
> + for_each_pipe(display, pipe) {
> + intel_de_rmw(display, DSPCNTR(display, pipe), 0,
> + DISP_TRICKLE_FEED_DISABLE);
> +
> + intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
> + intel_de_posting_read(display, DSPSURF(display, pipe));
> + }
> +}
> +
> +void intel_display_ilk_init_clock_gating(struct intel_display *display)
> +{
> + struct drm_i915_private *i915 = to_i915(display->drm);
> + u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> +
> + /*
> + * Required for FBC
> + * WaFbcDisableDpfcClockGating:ilk
> + */
> + dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> +
> + intel_de_write(display, PCH_3DCGDIS0,
> + MARIUNIT_CLOCK_GATE_DISABLE |
> + SVSMUNIT_CLOCK_GATE_DISABLE);
> + intel_de_write(display, PCH_3DCGDIS1, VFMUNIT_CLOCK_GATE_DISABLE);
Those two aren't display things.
> +
> + intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> + intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> + ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> + dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> + intel_de_write(display, DISP_ARB_CTL,
> + intel_de_read(display, DISP_ARB_CTL) |
> + DISP_FBC_WM_DIS);
> +
> + if (IS_IRONLAKE_M(i915)) {
> + /* WaFbcAsynchFlipDisableFbcQueue:ilk */
> + intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> + intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> + }
> +
> + intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> + intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +
> + intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_gen6_init_clock_gating(struct intel_display *display)
> +{
> + u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> +
> + intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
> + intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> +
> + intel_de_write(display, ILK_DISPLAY_CHICKEN1,
> + intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
> + ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> + intel_de_write(display, ILK_DISPLAY_CHICKEN2,
> + intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
> + ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> + intel_de_write(display, ILK_DSPCLK_GATE_D,
> + intel_de_read(display, ILK_DSPCLK_GATE_D) |
> + ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> +
> + intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_ivb_init_clock_gating(struct intel_display *display)
> +{
> + intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> + intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> +}
> +
> +void intel_display_g4x_init_clock_gating(struct intel_display *display)
> +{
> + struct drm_i915_private *i915 = to_i915(display->drm);
> + u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> + OVRUNIT_CLOCK_GATE_DISABLE |
> + OVCUNIT_CLOCK_GATE_DISABLE;
> +
> + if (IS_GM45(i915))
> + dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> +
> + intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
> +
> + intel_display_disable_trickle_feed(display);
> +}
> +
> +void intel_display_i965gm_init_clock_gating(struct intel_display *display)
> +{
> + intel_de_write(display, DSPCLK_GATE_D, 0);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> index 0eb240f2f69e..9eebfc4a6ebe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -17,6 +17,12 @@ void intel_display_glk_init_clock_gating(struct intel_display *display);
> void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display);
> void intel_display_bdw_init_clock_gating(struct intel_display *display);
> void intel_display_hsw_init_clock_gating(struct intel_display *display);
> +void intel_display_disable_trickle_feed(struct intel_display *display);
> +void intel_display_ilk_init_clock_gating(struct intel_display *display);
> +void intel_display_gen6_init_clock_gating(struct intel_display *display);
> +void intel_display_ivb_init_clock_gating(struct intel_display *display);
> +void intel_display_g4x_init_clock_gating(struct intel_display *display);
> +void intel_display_i965gm_init_clock_gating(struct intel_display *display);
> #else
> static inline void intel_display_skl_init_clock_gating(struct intel_display *display) {}
> static inline void intel_display_kbl_init_clock_gating(struct intel_display *display) {}
> @@ -26,6 +32,12 @@ static inline void intel_display_glk_init_clock_gating(struct intel_display *dis
> static inline void intel_display_bdw_hsw_init_clock_gating(struct intel_display *display) {}
> static inline void intel_display_bdw_init_clock_gating(struct intel_display *display) {}
> static inline void intel_display_hsw_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_disable_trickle_feed(struct intel_display *display) {}
> +static inline void intel_display_ilk_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_gen6_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_ivb_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_g4x_init_clock_gating(struct intel_display *display) {}
> +static inline void intel_display_i965gm_init_clock_gating(struct intel_display *display) {}
> #endif
>
> #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index a8e3eb6f06c8..98c048387a0a 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -29,11 +29,8 @@
> #include <drm/intel/intel_gmd_misc_regs.h>
> #include <drm/intel/intel_gmd_interrupt_regs.h>
>
> -#include "display/i9xx_plane_regs.h"
> -#include "display/intel_display.h"
> #include "display/intel_display_clock_gating.h"
> #include "display/intel_display_core.h"
> -#include "display/intel_display_regs.h"
> #include "gt/intel_engine_regs.h"
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_mcr.h"
> @@ -68,74 +65,9 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
> intel_display_glk_init_clock_gating(i915->display);
> }
>
> -static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> -{
> - struct intel_display *display = dev_priv->display;
> - enum pipe pipe;
> -
> - for_each_pipe(display, pipe) {
> - intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
> - 0, DISP_TRICKLE_FEED_DISABLE);
> -
> - intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
> - 0, 0);
> - intel_uncore_posting_read(&dev_priv->uncore,
> - DSPSURF(display, pipe));
> - }
> -}
> -
> static void ilk_init_clock_gating(struct drm_i915_private *i915)
> {
> - u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> - /*
> - * Required for FBC
> - * WaFbcDisableDpfcClockGating:ilk
> - */
> - dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> -
> - intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
> - MARIUNIT_CLOCK_GATE_DISABLE |
> - SVSMUNIT_CLOCK_GATE_DISABLE);
> - intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
> - VFMUNIT_CLOCK_GATE_DISABLE);
> -
> - /*
> - * According to the spec the following bits should be set in
> - * order to enable memory self-refresh
> - * The bit 22/21 of 0x42004
> - * The bit 5 of 0x42020
> - * The bit 15 of 0x45000
> - */
> - intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> - (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> - ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> - dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> - intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
> - (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
> - DISP_FBC_WM_DIS));
> -
> - /*
> - * Based on the document from hardware guys the following bits
> - * should be set unconditionally in order to enable FBC.
> - * The bit 22 of 0x42000
> - * The bit 22 of 0x42004
> - * The bit 7,8,9 of 0x42020.
> - */
> - if (IS_IRONLAKE_M(i915)) {
> - /* WaFbcAsynchFlipDisableFbcQueue:ilk */
> - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> - }
> -
> - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> -
> - g4x_disable_trickle_feed(i915);
> -
> + intel_display_ilk_init_clock_gating(i915->display);
> intel_pch_init_clock_gating(i915->display);
> }
>
> @@ -152,11 +84,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
>
> static void gen6_init_clock_gating(struct drm_i915_private *i915)
> {
> - u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> + intel_display_gen6_init_clock_gating(i915->display);
>
> intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
> intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
> @@ -191,19 +119,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
> *
> * WaFbcAsynchFlipDisableFbcQueue:snb
> */
> - intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
> - intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
> - ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> - intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> - intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> - ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
> - intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
> - ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
> - ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> -
> - g4x_disable_trickle_feed(i915);
> -
> intel_pch_init_clock_gating(i915->display);
>
> gen6_check_mch_setup(i915);
> @@ -338,10 +253,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
> {
> struct intel_display *display = i915->display;
>
> - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> -
> - /* WaFbcAsynchFlipDisableFbcQueue:ivb */
> - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> + intel_display_ivb_init_clock_gating(display);
>
> /* WaDisableBackToBackFlipFix:ivb */
> intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
> @@ -370,7 +282,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
> intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> - g4x_disable_trickle_feed(i915);
> + intel_display_disable_trickle_feed(display);
>
> intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
> GEN6_MBC_SNPCR_MED);
> @@ -443,21 +355,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
>
> static void g4x_init_clock_gating(struct drm_i915_private *i915)
> {
> - u32 dspclk_gate;
> -
> intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
> intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> GS_UNIT_CLOCK_GATE_DISABLE |
> CL_UNIT_CLOCK_GATE_DISABLE);
> intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
> - dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> - OVRUNIT_CLOCK_GATE_DISABLE |
> - OVCUNIT_CLOCK_GATE_DISABLE;
> - if (IS_GM45(i915))
> - dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> - intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
> -
> - g4x_disable_trickle_feed(i915);
> + intel_display_g4x_init_clock_gating(i915->display);
> }
>
> static void i965gm_init_clock_gating(struct drm_i915_private *i915)
> @@ -466,7 +369,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
>
> intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
> intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
> - intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
> + intel_display_i965gm_init_clock_gating(i915->display);
> intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
> intel_uncore_write16(uncore, DEUC, 0);
> intel_uncore_write(uncore,
> --
> 2.53.0
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2026-03-24 15:04 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 14:29 [PATCH 0/8] drm/i915: move more display dependencies from i915 Luca Coelho
2026-03-24 14:29 ` [PATCH 1/8] drm/i915: move SKL clock gating init to display Luca Coelho
2026-03-24 17:40 ` Jani Nikula
2026-03-31 11:59 ` Luca Coelho
2026-03-24 14:29 ` [PATCH 2/8] drm/i915: move KBL " Luca Coelho
2026-03-24 14:29 ` [PATCH 3/8] drm/i915/display: move CFL " Luca Coelho
2026-03-24 14:29 ` [PATCH 4/8] drm/i915/display: move BXT " Luca Coelho
2026-03-24 14:29 ` [PATCH 5/8] drm/i915/display: move GLK " Luca Coelho
2026-03-24 14:29 ` [PATCH 6/8] drm/i915/display: move HSW and BDW " Luca Coelho
2026-03-24 16:36 ` Ville Syrjälä
2026-03-31 10:03 ` Luca Coelho
2026-03-31 10:19 ` Ville Syrjälä
2026-03-31 10:23 ` Luca Coelho
2026-03-24 14:29 ` [PATCH 7/8] drm/i915/display: move pre-HSW " Luca Coelho
2026-03-24 15:04 ` Ville Syrjälä [this message]
2026-03-24 15:26 ` Luca Coelho
2026-03-24 14:29 ` [PATCH 8/8] drm/i915: remove HAS_PCH_NOP() dependency from clock gating Luca Coelho
2026-03-24 17:06 ` ✗ Fi.CI.BUILD: failure for drm/i915: move more display dependencies from i915 Patchwork
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