From: rajpat@codeaurora.org
To: Stephen Boyd <swboyd@chromium.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, rnayak@codeaurora.org,
saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com,
skakit@codeaurora.org, mka@chromium.org, dianders@chromium.org,
Roja Rani Yarubandi <rojay@codeaurora.org>
Subject: Re: [PATCH V8 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
Date: Tue, 21 Sep 2021 09:33:57 +0530 [thread overview]
Message-ID: <aca568eb87d0f3b95fcf35f956613f4f@codeaurora.org> (raw)
In-Reply-To: <CAE-0n51JdKDSDKhbhQSbF5w=cn5iQ_uRDG0-NMR+FPdGkuX4UA@mail.gmail.com>
On 2021-09-21 01:12, Stephen Boyd wrote:
> Quoting Rajesh Patil (2021-09-17 02:48:03)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 2fbcb0a..a2a4d7e 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -536,24 +536,444 @@
>> qupv3_id_0: geniqup@9c0000 {
>> compatible = "qcom,geni-se-qup";
>> reg = <0 0x009c0000 0 0x2000>;
>> - clock-names = "m-ahb", "s-ahb";
>> clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>> <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
>> + clock-names = "m-ahb", "s-ahb";
>> #address-cells = <2>;
>> #size-cells = <2>;
>> ranges;
>> + iommus = <&apps_smmu 0x123 0x0>;
>> status = "disabled";
>>
>> + qup_opp_table: qup-opp-table {
>
> Sorry to mislead you. I see now why it can't be here. qeniqup has
> address cells and size cells not equal to zero, which means that every
> child node of qeniqup should have a reg property. So this OPP table
> needs to be moved to the root again (ugh).
Okay
>
>> + compatible = "operating-points-v2";
>> +
>> + opp-75000000 {
>> + opp-hz = /bits/ 64 <75000000>;
>> + required-opps =
>> <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-100000000 {
>> + opp-hz = /bits/ 64
>> <100000000>;
>> + required-opps =
>> <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-128000000 {
>> + opp-hz = /bits/ 64
>> <128000000>;
>> + required-opps =
>> <&rpmhpd_opp_nom>;
>> + };
>> + };
>> +
>> + i2c0: i2c@980000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00980000 0 0x4000>;
>> + clocks = <&gcc
>> GCC_QUPV3_WRAP0_S0_CLK>;
>> + clock-names = "se";
>> + pinctrl-names = "default";
> [...]
>>
>> cnoc2: interconnect@1500000 {
>> @@ -1574,11 +1994,311 @@
>> function = "qspi_data";
> [...]
>> +
>> + qup_spi0_cs_gpio: qup-spi0-cs_gpio {
>
> Please make it "qup_spi0_cs_gpio: qup-spi0-cs-gpio" as node names
> should
> have dashes instead of underscores.
Okay
>
>> + pins = "gpio3";
next prev parent reply other threads:[~2021-09-21 4:04 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 9:47 [PATCH V8 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-09-17 9:48 ` [PATCH V8 1/8] dt-bindings: spi: Add sc7280 support Rajesh Patil
2021-09-17 19:48 ` Rob Herring
2021-09-17 20:02 ` Doug Anderson
2021-09-21 4:04 ` rajpat
2021-09-21 6:23 ` rajpat
2021-09-17 9:48 ` [PATCH V8 2/8] arm64: dts: sc7280: Add QSPI node Rajesh Patil
2021-09-20 19:38 ` Stephen Boyd
2021-09-17 9:48 ` [PATCH V8 3/8] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
2021-09-17 9:48 ` [PATCH V8 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
2021-09-20 19:42 ` Stephen Boyd
2021-09-21 4:03 ` rajpat [this message]
2021-09-17 9:48 ` [PATCH V8 5/8] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
2021-09-20 19:43 ` Stephen Boyd
2021-09-17 9:48 ` [PATCH V8 6/8] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
2021-09-20 19:44 ` Stephen Boyd
2021-09-17 9:48 ` [PATCH V8 7/8] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
2021-09-20 19:45 ` Stephen Boyd
2021-09-17 9:48 ` [PATCH V8 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI Rajesh Patil
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