From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, mika.kahola@intel.com
Subject: Re: [PATCH 14/14] drm/i915: Modeset global_pipes() update
Date: 17 Apr 2015 02:23:25 -0700 [thread overview]
Message-ID: <acb6cf$l5q4lk@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1429103244-3515-15-git-send-email-mika.kahola@intel.com>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6220
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 318/318 318/318
IVB 341/341 341/341
BYT 287/287 287/287
HSW -2 395/395 393/395
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
HSW igt@gem_pwrite_pread@snooped-copy-performance DMESG_WARN(1)PASS(5) DMESG_WARN(2)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
HSW igt@gem_pwrite_pread@snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1)PASS(7) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-04-17 9:23 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-15 13:07 All sort of cdclk stuff Mika Kahola
2015-04-15 13:07 ` [PATCH 01/14] drm/i915: Fix i855 get_display_clock_speed Mika Kahola
2015-04-15 13:07 ` [PATCH 02/14] drm/i915: Fix 852GM/GMV cdclk Mika Kahola
2015-04-15 13:07 ` [PATCH 03/14] drm/i915: Add cdclk extraction for g33, g965gm and g4x Mika Kahola
2015-04-15 13:07 ` [PATCH 04/14] drm/i915: Warn when cdclk for the platforms is not known Mika Kahola
2015-04-15 13:07 ` [PATCH 05/14] drm/i915: Cache current cdclk frequency in dev_priv Mika Kahola
2015-04-15 13:07 ` [PATCH 06/14] drm/i915: Use cached cdclk value Mika Kahola
2015-04-15 13:07 ` [PATCH 07/14] drm/i915: Unify ilk and hsw .get_aux_clock_divider Mika Kahola
2015-04-15 13:07 ` [PATCH 08/14] drm/i915: Store max cdclk value in dev_priv Mika Kahola
2015-04-15 13:07 ` [PATCH 09/14] drm/i915: Don't enable IPS when pixel rate exceeds 95% Mika Kahola
2015-04-15 13:07 ` [PATCH 10/14] drm/i915: HSW cdclk support Mika Kahola
2015-04-15 13:07 ` [PATCH 11/14] drm/i915: Add IS_BDW_ULX Mika Kahola
2015-04-15 13:07 ` [PATCH 12/14] drm/i915: BDW clock change support Mika Kahola
2015-04-15 13:07 ` [PATCH 13/14] drm/i915: Limit CHV max cdclk Mika Kahola
2015-04-15 19:19 ` Ville Syrjälä
2015-04-15 13:07 ` [PATCH 14/14] drm/i915: Modeset global_pipes() update Mika Kahola
2015-04-15 19:19 ` Ville Syrjälä
2015-04-17 9:23 ` shuang.he [this message]
2015-04-15 13:16 ` All sort of cdclk stuff Damien Lespiau
2015-04-15 13:58 ` Mika Kahola
2015-04-15 14:18 ` Ville Syrjälä
2015-04-16 13:11 ` Jani Nikula
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