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From: Raag Jadav <raag.jadav@intel.com>
To: Riana Tauro <riana.tauro@intel.com>
Cc: intel-xe@lists.freedesktop.org, anshuman.gupta@intel.com,
	rodrigo.vivi@intel.com, aravind.iddamsetty@linux.intel.com,
	badal.nilawar@intel.com, ravi.kishore.koppuravuri@intel.com,
	mallesh.koujalagi@intel.com
Subject: Re: [PATCH 3/5] drm/xe/ras: Add flag for Xe RAS
Date: Wed, 1 Apr 2026 09:53:48 +0200	[thread overview]
Message-ID: <aczPDEvv1w4HGqFH@black.igk.intel.com> (raw)
In-Reply-To: <20260320102607.1017511-4-riana.tauro@intel.com>

On Fri, Mar 20, 2026 at 03:55:58PM +0530, Riana Tauro wrote:
> Add a flag for RAS. If enabled, XE driver registers with
> DRM RAS and exposes supported counters.
> 
> Currently this is enabled for PVC and CRI.

This looks like it should be the last patch in the series.

Raag

> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>  drivers/gpu/drm/xe/xe_hw_error.c     | 2 +-
>  drivers/gpu/drm/xe/xe_pci.c          | 3 +++
>  drivers/gpu/drm/xe/xe_pci_types.h    | 1 +
>  4 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 150c76b2acaf..bfb23d6c0511 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -191,6 +191,8 @@ struct xe_device {
>  		u8 has_ctx_tlb_inval:1;
>  		/** @info.has_range_tlb_inval: Has range based TLB invalidations */
>  		u8 has_range_tlb_inval:1;
> +		/** @info.has_ras: Device supports RAS (Reliability, Availability, Serviceability) */
> +		u8 has_ras:1;
>  		/** @info.has_soc_remapper_sysctrl: Has SoC remapper system controller */
>  		u8 has_soc_remapper_sysctrl:1;
>  		/** @info.has_soc_remapper_telem: Has SoC remapper telemetry support */
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 2a31b430570e..3ab0fceb151f 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -520,7 +520,7 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
>  
>  static int hw_error_info_init(struct xe_device *xe)
>  {
> -	if (xe->info.platform != XE_PVC)
> +	if (!xe->info.has_ras)
>  		return 0;
>  
>  	return xe_drm_ras_init(xe);
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index f5dd77b6680f..e44003b5aee3 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -364,6 +364,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
>  	.vm_max_level = 4,
>  	.vram_flags = XE_VRAM_FLAGS_NEED64K,
>  	.has_mbx_power_limits = false,
> +	.has_ras = true,
>  };
>  
>  static const struct xe_device_desc mtl_desc = {
> @@ -471,6 +472,7 @@ static const struct xe_device_desc cri_desc = {
>  	.require_force_probe = true,
>  	.va_bits = 57,
>  	.vm_max_level = 4,
> +	.has_ras = true,
>  };
>  
>  static const struct xe_device_desc nvlp_desc = {
> @@ -761,6 +763,7 @@ static int xe_info_init_early(struct xe_device *xe,
>  	xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
>  	xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
>  	xe->info.has_pxp = desc->has_pxp;
> +	xe->info.has_ras = desc->has_ras;
>  	xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl;
>  	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
>  	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 08386c5eca27..cb7d79f51753 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -54,6 +54,7 @@ struct xe_device_desc {
>  	u8 has_pre_prod_wa:1;
>  	u8 has_page_reclaim_hw_assist:1;
>  	u8 has_pxp:1;
> +	u8 has_ras:1;
>  	u8 has_soc_remapper_sysctrl:1;
>  	u8 has_soc_remapper_telem:1;
>  	u8 has_sriov:1;
> -- 
> 2.47.1
> 

  reply	other threads:[~2026-04-01  7:53 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-20 10:25 [PATCH 0/5] Add get-error-counter support for CRI Riana Tauro
2026-03-20 10:25 ` [PATCH 1/5] drm/xe/xe_sysctrl: Add System controller patch Riana Tauro
2026-03-20 10:25 ` [PATCH 2/5] drm/xe/uapi: Add additional error components to XE DRM RAS Riana Tauro
2026-03-25  9:24   ` Aravind Iddamsetty
2026-03-20 10:25 ` [PATCH 3/5] drm/xe/ras: Add flag for Xe RAS Riana Tauro
2026-04-01  7:53   ` Raag Jadav [this message]
2026-04-06  5:25     ` Tauro, Riana
2026-03-20 10:25 ` [PATCH 4/5] drm/xe/xe_ras: Add structures and commands for get counter Riana Tauro
2026-04-01  7:58   ` Raag Jadav
2026-04-06  5:23     ` Tauro, Riana
2026-04-07  7:45       ` Raag Jadav
2026-04-07  7:58         ` Tauro, Riana
2026-03-20 10:26 ` [PATCH 5/5] drm/xe/xe_ras: Add support to query error counter for CRI Riana Tauro
2026-04-01  8:08   ` Raag Jadav
2026-04-06  7:29     ` Tauro, Riana
2026-03-20 10:33 ` ✗ CI.checkpatch: warning for Add get-error-counter support " Patchwork
2026-03-20 10:35 ` ✓ CI.KUnit: success " Patchwork
2026-03-20 11:16 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-03-21  8:10 ` ✓ Xe.CI.FULL: success " Patchwork

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