Re: [PATCH] cxl/region: fix x9 interleave typo

[Dave Jiang <dave.jiang@intel.com>]

On 11/3/23 13:18, Jim Harris wrote:
> CXL supports x3, x6 and x12 - not x9.
> 
> Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
> Signed-off-by: Jim Harris <jim.harris@samsung.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

Given it's a fix to a comment, the fixes tag is probably not necessary since it's not a code bug to backport to stable. 

> ---
>  drivers/cxl/core/region.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6d63b8798c29..d295b3488e4a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
>  		return rc;
>  
>  	/*
> -	 * Even for x3, x9, and x12 interleaves the region interleave must be a
> +	 * Even for x3, x6, and x12 interleaves the region interleave must be a
>  	 * power of 2 multiple of the host bridge interleave.
>  	 */
>  	if (!is_power_of_2(val / cxld->interleave_ways) ||
>