From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Shiji Yang <yangshiji66@outlook.com>
Cc: linux-mips@vger.kernel.org,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH 1/3] mips: pci-mt7620: fix bridge register access
Date: Mon, 6 Apr 2026 14:28:48 +0200 [thread overview]
Message-ID: <adOnAAkIuuMAro1U@alpha.franken.de> (raw)
In-Reply-To: <OSBPR01MB1670555F549B69B9A5E7F133BC72A@OSBPR01MB1670.jpnprd01.prod.outlook.com>
On Wed, Jun 18, 2025 at 11:42:05AM +0800, Shiji Yang wrote:
> Host bridge registers and PCI RC control registers have different
> memory base. pcie_m32() is used to write the RC control registers
> instead of bridge registers. This patch introduces bridge_m32()
> and use it to operate bridge registers to fix the access issue.
>
> Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
> ---
> arch/mips/pci/pci-mt7620.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
applied to mips-next
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
prev parent reply other threads:[~2026-04-06 12:35 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 3:42 [PATCH 1/3] mips: pci-mt7620: fix bridge register access Shiji Yang
2025-06-18 3:42 ` [PATCH 2/3] mips: pci-mt7620: add more register init values Shiji Yang
2026-04-06 12:29 ` Thomas Bogendoerfer
2025-06-18 3:42 ` [PATCH 3/3] mips: pci-mt7620: rework initialization procedure Shiji Yang
2026-04-06 12:29 ` Thomas Bogendoerfer
2026-02-24 1:14 ` [PATCH 1/3] mips: pci-mt7620: fix bridge register access Shiji Yang
2026-04-06 12:28 ` Thomas Bogendoerfer [this message]
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