Re: [PATCH 09/13] Core WQE/CQE Types

[Roland Dreier <rdreier@cisco.com>]

 > +struct t3_send_wr {
 > +	struct fw_riwrh wrh;	/* 0 */
 > +	union t3_wrid wrid;	/* 1 */
 > +
 > +	enum t3_rdma_opcode rdmaop:8;
 > +	u32 reserved:24;	/* 2 */

Does this do the right thing wrt endianness?  I'd be more comfortable
with something like

	u8 rdmaop;
        u8 reserved[3];

(although the __attribute__((packed)) on enum t3_rdma_opcode does make
it OK to use here, I guess)

 > +	u32 rem_stag;		/* 2 */
 > +	u32 plen;		/* 3 */
 > +	u32 num_sgle;
 > +	struct t3_sge sgl[T3_MAX_SGE];	/* 4+ */
 > +};