Re: [PATCH v2 5/9] target/riscv: Use the tb->cs_bqse as the extend tb flags.

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

Note: typo in commit title: 'cs->bqse'

On 1/8/2026 10:26 AM, Max Chou wrote:
> We have more than 32-bits worth of state per TB, so use the
> tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

That's a neat idea. I'll use it in my e-trace series in case this series
is merged first.


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>


>   include/exec/translation-block.h | 1 +
>   target/riscv/cpu.h               | 3 +++
>   target/riscv/tcg/tcg-cpu.c       | 7 ++++++-
>   3 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
> index 4f83d5bec9..40cc699031 100644
> --- a/include/exec/translation-block.h
> +++ b/include/exec/translation-block.h
> @@ -65,6 +65,7 @@ struct TranslationBlock {
>        * arm: an extension of tb->flags,
>        * s390x: instruction data for EXECUTE,
>        * sparc: the next pc of the instruction queue (for delay slots).
> +     * riscv: an extension of tb->flags,
>        */
>       uint64_t cs_base;
>   
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 962cc45073..4c0676ed53 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)
>   FIELD(TB_FLAGS, PM_PMM, 29, 2)
>   FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)
>   
> +FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)
> +FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)
> +
>   #ifdef TARGET_RISCV32
>   #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>   #else
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 720ff0c2a3..378b298886 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>       RISCVCPU *cpu = env_archcpu(env);
>       RISCVExtStatus fs, vs;
>       uint32_t flags = 0;
> +    uint64_t ext_flags = 0;
>       bool pm_signext = riscv_cpu_virt_mem_enabled(env);
>   
>       if (cpu->cfg.ext_zve32x) {
> @@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>   
>           /* lmul encoded as in DisasContext::lmul */
>           int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
> +        uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);
>           uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
>           uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
>           uint32_t maxsz = vlmax << vsew;
> @@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>           flags = FIELD_DP32(flags, TB_FLAGS, VMA,
>                              FIELD_EX64(env->vtype, VTYPE, VMA));
>           flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
> +        ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt);
>       } else {
>           flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
>       }
> @@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>       flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
>       flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
>   
> +    ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext);
> +
>       return (TCGTBCPUState){
>           .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,
>           .flags = flags,
> -        .cs_base = env->misa_ext,
> +        .cs_base = ext_flags,
>       };
>   }
>