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Fri, 17 Apr 2026 02:53:13 -0700 (PDT) Received: from linaro.org ([2a10:d582:31e:0:d023:c0db:d3ea:590d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fc1c96b4sm52427845e9.13.2026.04.17.02.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 02:53:13 -0700 (PDT) Date: Fri, 17 Apr 2026 10:53:12 +0100 From: Jim MacArthur To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: Re: [PATCH 2/3] target/arm/ptw.c: Add two new spaces to the granule protection case Message-ID: References: <20260416-jmac-feat_rme_gdi-v1-0-d9fa0781ed58@linaro.org> <20260416-jmac-feat_rme_gdi-v1-2-d9fa0781ed58@linaro.org> <5fb0432b-6c1c-40bc-b022-939d73f2115d@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5fb0432b-6c1c-40bc-b022-939d73f2115d@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Apr 17, 2026 at 08:36:52AM +1000, Richard Henderson wrote: > On 4/16/26 21:12, Jim MacArthur wrote: > > This makes no functional difference, it just marks out two cases for > > future use. > > > > Signed-off-by: Jim MacArthur > > --- > > target/arm/ptw.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > > index 7b993bb5b3..d4b63a365a 100644 > > --- a/target/arm/ptw.c > > +++ b/target/arm/ptw.c > > @@ -510,6 +510,11 @@ bool arm_granule_protection_check(ARMGranuleProtectionConfig config, > > break; > > case 0b1111: /* all access */ > > return true; > > + case 0b0100: /* system agent only */ > > + case 0b0101: /* non-secure protected */ > > + /* System Agent and Non-secure Protected are GDI extensions. */ > > + /* No processing element should have access to these. */ > > + goto fault_walk; > > case 0b1000: /* secure */ > > if (!config.support_sel2) { > > goto fault_walk; > > > > There's no real point to this patch, since we get the same effect from the default case. > > It should be trivial to "properly" implement these two cases for the CPU, since > > R_QCLPTA: PE is not permitted to access memory within the NSP > or the SA PA spaces, from any Security state. > > Access to these spaces is only allowed from external devices via the SMMU. > > The only effect on the PE is to check the various GPCCR fields (SA, NSP, > NA6, NA7) to transform them from one type of fault to another: fault_walk -> > fault_fail (i.e. break). The thing that held me back here was the mapping from 'Reserved' in the table in D9.6.5 to fault_walk, which wasn't clear in the documentation, and hence leaving the behaviour unchanged. However, I would agree that we can map (GPCCR.SA=1, gpi=0x0x100) to fault_fail and so on and leave the (SA=0, 0b0100) case to what it would have been before (fault_walk). Thanks for your feedback, Jim