From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA737374FE for ; Thu, 30 Nov 2023 09:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from dggems704-chm.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Sgr913zmMz1FDCJ; Thu, 30 Nov 2023 17:13:57 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by dggems704-chm.china.huawei.com (10.3.19.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Nov 2023 17:17:18 +0800 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.035; Thu, 30 Nov 2023 09:17:16 +0000 From: Shameerali Kolothum Thodi To: Jason Gunthorpe CC: "iommu@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "robin.murphy@arm.com" , "will@kernel.org" , "joro@8bytes.org" , "kevin.tian@intel.com" , "nicolinc@nvidia.com" , "mshavit@google.com" , "eric.auger@redhat.com" , "joao.m.martins@oracle.com" , jiangkunkun , zhukeqian , Linuxarm Subject: RE: [PATCH 2/5] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping Thread-Topic: [PATCH 2/5] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping Thread-Index: AQHaIeBRc93JC1IpIk+TwCcyXKVIvbCRsV0AgADmc9A= Date: Thu, 30 Nov 2023 09:17:16 +0000 Message-ID: References: <20231128094940.1344-1-shameerali.kolothum.thodi@huawei.com> <20231128094940.1344-3-shameerali.kolothum.thodi@huawei.com> <20231129193050.GA436702@nvidia.com> In-Reply-To: <20231129193050.GA436702@nvidia.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CFilter-Loop: Reflected > -----Original Message----- > From: Jason Gunthorpe > Sent: Wednesday, November 29, 2023 7:31 PM > To: Shameerali Kolothum Thodi > Cc: iommu@lists.linux.dev; linux-arm-kernel@lists.infradead.org; > robin.murphy@arm.com; will@kernel.org; joro@8bytes.org; > kevin.tian@intel.com; nicolinc@nvidia.com; mshavit@google.com; > eric.auger@redhat.com; joao.m.martins@oracle.com; jiangkunkun > ; zhukeqian ; Linuxarm > > Subject: Re: [PATCH 2/5] iommu/arm-smmu-v3: Enable HTTU for stage1 with i= o- > pgtable mapping >=20 > On Tue, Nov 28, 2023 at 09:49:37AM +0000, Shameer Kolothum wrote: >=20 > > /* IOMMU API */ > > static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) > > { > > @@ -2401,6 +2413,10 @@ static int arm_smmu_domain_finalise(struct > arm_smmu_domain *smmu_domain, > > .iommu_dev =3D smmu->dev, > > }; > > > > + if (arm_smmu_dbm_capable(smmu) && > > + smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) > > + pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_HD; > > + >=20 > This flow has become a bit wonky, the switch statement right above is > already checking S1 and partially initializing pgtbl_cfg. >=20 > I suggest moving the pgtbl_cfg init to above the switch and making the > switch store directly into pgtbl_cfg values and remove the stack ios > and oas values >=20 Got it. Will do. Thanks, Shameer From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B04F9C4167B for ; Thu, 30 Nov 2023 09:18:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iCUpcQV3oViZrqFs1nwjf0P1O+jD/uA4REqKpJIqkP0=; b=zCd53gUOItSzZC Symk/YpHHqeJ1RQOUIEOJr0trYTX2aLLz5pFRl3Uke8KQjtiU5owKuvrzO7Fmxr/JQ1Kk7xO0i7DJ Rd+NvgA5B0O8PaGfl7oTLtwJubJ4RresqXak5jeH/RQhnxGhvGHEcnhE6mPGywtecbg8UPKVdAPfH 4JEiGc9VlF/F9LUtxe3vhUueM7G2edL7eZJmOueVf+nmyF4bbVfrbMTUwH8wew/9zjh9nyR+b1o3k cSlynh189DQAyHcletYEL/30EVBpB4dGBrGn4PzhVpxV9IruO2nRiSWTuymPiUS3XytjA31Erq0tw +MuWdMUh4OrAzR+XevZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r8dAp-00AJ62-2U; Thu, 30 Nov 2023 09:17:31 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r8dAm-00AJ5O-1N for linux-arm-kernel@lists.infradead.org; Thu, 30 Nov 2023 09:17:30 +0000 Received: from dggems704-chm.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Sgr913zmMz1FDCJ; Thu, 30 Nov 2023 17:13:57 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by dggems704-chm.china.huawei.com (10.3.19.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Nov 2023 17:17:18 +0800 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.035; Thu, 30 Nov 2023 09:17:16 +0000 From: Shameerali Kolothum Thodi To: Jason Gunthorpe CC: "iommu@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "robin.murphy@arm.com" , "will@kernel.org" , "joro@8bytes.org" , "kevin.tian@intel.com" , "nicolinc@nvidia.com" , "mshavit@google.com" , "eric.auger@redhat.com" , "joao.m.martins@oracle.com" , jiangkunkun , zhukeqian , Linuxarm Subject: RE: [PATCH 2/5] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping Thread-Topic: [PATCH 2/5] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping Thread-Index: AQHaIeBRc93JC1IpIk+TwCcyXKVIvbCRsV0AgADmc9A= Date: Thu, 30 Nov 2023 09:17:16 +0000 Message-ID: References: <20231128094940.1344-1-shameerali.kolothum.thodi@huawei.com> <20231128094940.1344-3-shameerali.kolothum.thodi@huawei.com> <20231129193050.GA436702@nvidia.com> In-Reply-To: <20231129193050.GA436702@nvidia.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.28] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231130_011728_628943_3B9DC393 X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Jason Gunthorpe > Sent: Wednesday, November 29, 2023 7:31 PM > To: Shameerali Kolothum Thodi > Cc: iommu@lists.linux.dev; linux-arm-kernel@lists.infradead.org; > robin.murphy@arm.com; will@kernel.org; joro@8bytes.org; > kevin.tian@intel.com; nicolinc@nvidia.com; mshavit@google.com; > eric.auger@redhat.com; joao.m.martins@oracle.com; jiangkunkun > ; zhukeqian ; Linuxarm > > Subject: Re: [PATCH 2/5] iommu/arm-smmu-v3: Enable HTTU for stage1 with io- > pgtable mapping > > On Tue, Nov 28, 2023 at 09:49:37AM +0000, Shameer Kolothum wrote: > > > /* IOMMU API */ > > static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) > > { > > @@ -2401,6 +2413,10 @@ static int arm_smmu_domain_finalise(struct > arm_smmu_domain *smmu_domain, > > .iommu_dev = smmu->dev, > > }; > > > > + if (arm_smmu_dbm_capable(smmu) && > > + smmu_domain->stage == ARM_SMMU_DOMAIN_S1) > > + pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_HD; > > + > > This flow has become a bit wonky, the switch statement right above is > already checking S1 and partially initializing pgtbl_cfg. > > I suggest moving the pgtbl_cfg init to above the switch and making the > switch store directly into pgtbl_cfg values and remove the stack ios > and oas values > Got it. Will do. Thanks, Shameer _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel