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[203.214.45.63]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8e985a72sm13908824b3a.11.2026.04.21.02.10.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 02:10:35 -0700 (PDT) Date: Tue, 21 Apr 2026 19:10:31 +1000 From: Nicholas Piggin To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Joel Stanley , Alistair Francis , Daniel Henrique Barboza , Michael Ellerman , Joel Stanley , Anirudh Srinivasan , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v3 10/13] hw/riscv/atlantis: Add PCIe controller Message-ID: References: <20260421053140.752059-1-joel@jms.id.au> <20260421053140.752059-11-joel@jms.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Apr 21, 2026 at 07:59:32AM +0200, Philippe Mathieu-Daudé wrote: > On 21/4/26 07:31, Joel Stanley wrote: > > From: Nicholas Piggin > > > > tt-atlantis is likely to use a generic ECAM compatible PCIe memory map, > > so gpex is not far off the OS programming model > > > > Signed-off-by: Nicholas Piggin > > Signed-off-by: Joel Stanley > > --- > > v3: Avoid leaks in the dt string allocation > > --- > > include/hw/riscv/tt_atlantis.h | 2 + > > hw/riscv/tt_atlantis.c | 225 ++++++++++++++++++++++++++++++++- > > hw/riscv/Kconfig | 2 + > > 3 files changed, 228 insertions(+), 1 deletion(-) > > > > +static void create_fdt_pcie(void *fdt, > > + const MemMapEntry *mem_ecam, > > + const MemMapEntry *mem_pio, > > + const MemMapEntry *mem_mmio32, > > + const MemMapEntry *mem_mmio64, > > + int legacy_irq, > > + uint32_t aplic_s_phandle, > > + uint32_t imsic_s_phandle) > > +{ > > + g_autofree char *name = g_strdup_printf("/soc/pci@%"HWADDR_PRIX, > > + mem_ecam->base); > > + > > + qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); > > + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); > > + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); > > + qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); > > + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); > > + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, > > + mem_ecam->size / PCIE_MMCFG_SIZE_MIN - 1); > > + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); > > + qemu_fdt_setprop_cell(fdt, name, "msi-parent", imsic_s_phandle); > > + > > + qemu_fdt_setprop_sized_cells(fdt, name, "reg", > > + 2, mem_ecam->base, > > + 2, mem_ecam->size); > > + if (!(mem_mmio32->base & 0xffffffffUL)) { > > + /* XXX: this is a silly hack because it would collide with PIO */ > > Could you explain a bit more? Ah this is a bit incomplete sorry I didn't catch it earlier. Before the mapping was finalised I just added this hacky way to determining PCIe IO address based on the physical address. This should just go away and the IO addresses come from a different table. > > > + error_report("mmio32 base must not be 0 mod 2^32"); > > + exit(1); > > + } > > + uint32_t flags = FDT_PCI_RANGE_MMIO_64BIT | FDT_PCI_RANGE_PREFETCHABLE; > > + qemu_fdt_setprop_sized_cells(fdt, name, "ranges", > > + 1, FDT_PCI_RANGE_IOPORT, > > + 2, 0x0, > > + 2, mem_pio->base, > > + 2, mem_pio->size, > > + 1, FDT_PCI_RANGE_MMIO, > > + 2, (mem_mmio32->base & 0xffffffffUL), > > + 2, mem_mmio32->base, > > + 2, mem_mmio32->size, > > + 1, flags, > > + 2, mem_mmio64->base, > > + 2, mem_mmio64->base, > > + 2, mem_mmio64->size); > > + > > + create_pcie_irq_map(fdt, name, legacy_irq, aplic_s_phandle); > > +} > > > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > > index 0601ae1a7494..2ddee591eb90 100644 > > --- a/hw/riscv/Kconfig > > +++ b/hw/riscv/Kconfig > > @@ -129,6 +129,8 @@ config TENSTORRENT > > select DEVICE_TREE > > select RISCV_NUMA > > select PVPANIC_MMIO > > + select PCI > > Do not select PCI explicitly, let the bridge (below) do it. > Rationale is this machine does not expose a PCI bus directly, > the bridge device does. Good to know, thank you. Thanks, Nick