From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 14/16] intel: Add is_855ish for handling 855 and 865 specific lod clamping Date: Tue, 07 Jun 2011 21:22:28 +0100 Message-ID: References: <1307475261-32695-1-git-send-email-krh@bitplanet.net> <1307475261-32695-15-git-send-email-krh@bitplanet.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0323455704==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 302EE9E799 for ; Tue, 7 Jun 2011 13:22:49 -0700 (PDT) In-Reply-To: <1307475261-32695-15-git-send-email-krh@bitplanet.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0323455704== Content-Type: text/plain On Tue, 7 Jun 2011 15:34:19 -0400, Kristian Høgsberg wrote: > struct intel_chipset { > int gen; > - GLboolean is_945, is_g4x; > + GLboolean is_855ish, is_945, is_g4x; > > /* WM maximum threads is number of EUs times number of threads per EU. */ > int wm_max_threads; This can be handled by adding a few more bits per-gen. I found using 20 830/845 21 855/865 30 915 31 945 33 g33 + pnv 40 965 45 g4x 50 ilk 60 snb ...to infinity and beyond... works quite well for specifying render capabilities for gen2/3/4. Can these structs and pci-id tables be reused by projects external to mesa? -Chris -- Chris Wilson, Intel Open Source Technology Centre --===============0323455704== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0323455704==--