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Thu, 07 May 2026 20:54:39 -0700 (PDT) Received: from localhost ([1.146.100.102]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d271b7sm4430135ad.14.2026.05.07.20.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 20:54:39 -0700 (PDT) Date: Fri, 8 May 2026 13:54:30 +1000 From: Nicholas Piggin To: Andrew Jones Cc: Alistair Francis , Daniel Henrique Barboza , Chao Liu , Michael Ellerman , Joel Stanley , Anirudh Srinivasan , Portia Stephens , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Subject: Re: [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade Message-ID: References: <20260507043838.45652-1-npiggin@gmail.com> <20260507043838.45652-7-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=npiggin@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, May 07, 2026 at 01:57:02PM -0500, Andrew Jones wrote: > On Thu, May 07, 2026 at 02:38:34PM +1000, Nicholas Piggin wrote: > > Ascalon supports Svadu (hardware A/D bit updates). > > > > QEMU makes Svadu and Svade mutually exclusive, remove Svade so > > Ascalon comes up with Svadu working. > > Hi Nicholas, > > Svadu and Svade aren't mutually exclusive, you can see the expected > behaviors for the pair in the commit message of commit 70d22fd92c3b > ("target/riscv: Gate hardware A/D PTE bit updating"). Okay misunderstood what QEMU is doing. What does it mean for an implementation to support Svadu && !Svade? AFAIKS the spec says ADUE=0 means the access is performed as though Svade is implemented. I'm either wrong about that or miss the point why Svadu && Svade is handled differently in the patch you reference (or both). > Does the > Ascalon support Svade? If so, then it's probably best to enable both > and leave it to Linux to enable Svadu with SBI FWFT > SBI_FWFT_PTE_AD_HW_UPDATING in order to maximize the amount of > software supported. But, unfortunately Linux doesn't yet support the > checking for and enabling of SBI_FWFT_PTE_AD_HW_UPDATING. We still > need kernel patches for that. Our docs say it supports both. If enabling both bits is the correct thing to do we should go with that for upstream. Thanks, Nick