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Sat, 05 Apr 2025 02:20:35 -0700 (PDT) Received: from [192.168.68.110] ([177.170.227.223]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-229785c0218sm45874645ad.89.2025.04.05.02.20.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Apr 2025 02:20:34 -0700 (PDT) Message-ID: Date: Sat, 5 Apr 2025 06:20:31 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions To: Max Chou , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , antonb@tenstorrent.com References: <20250329144446.2619306-1-max.chou@sifive.com> <20250329144446.2619306-11-max.chou@sifive.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250329144446.2619306-11-max.chou@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 3/29/25 11:44 AM, Max Chou wrote: > Handle the overlap of source registers with different EEWs. > > Co-authored-by: Anton Blanchard > Co-authored-by: Max Chou > Signed-off-by: Max Chou > --- With your co-authored-by tag removed: Reviewed-by: Daniel Henrique Barboza > target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index f30157939b8..d4d1ad055fa 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -585,7 +585,8 @@ static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm) > > static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) > { > - bool ret = vext_narrow_check_common(s, vd, vs, vm); > + bool ret = vext_narrow_check_common(s, vd, vs, vm) && > + vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm); > if (vd != vs) { > ret &= require_noover(vd, s->lmul, vs, s->lmul + 1); > } > @@ -608,6 +609,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) > static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm) > { > return vext_check_sd(s, vd, vs2, vm) && > + vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) && > require_align(vs1, s->lmul); > } >