From: Zenghui Yu <zenghui.yu@linux.dev>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org,
Mohamed Mediouni <mohamed@unpredictable.fr>,
qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Alexander Graf <agraf@csgraf.de>,
Cameron Esfahani <dirty@apple.com>, Mads Ynddal <mads@ynddal.dk>,
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Subject: Re: [PATCH v5 2/2] target/arm/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0
Date: Thu, 12 Feb 2026 23:05:06 +0800 [thread overview]
Message-ID: <af89e56b-1d08-457c-ac1e-8a94cf47c176@linux.dev> (raw)
In-Reply-To: <20260118215945.46693-3-philmd@linaro.org>
Hi,
On 1/19/26 5:59 AM, Philippe Mathieu-Daudé wrote:
> Keep CNTV_CTL_EL0 and CNTV_CVAL_EL0 synchronized with the
> host hardware accelerator.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/arm/hvf/hvf.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index fcb7fa3b30c..9ce720793d8 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -200,6 +200,9 @@ void hvf_arm_init_debug(void)
> #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6)
> #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7)
> #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
> +
> +#define SYSREG_CNTV_CTL_EL0 SYSREG(3, 3, 14, 3, 1)
> +#define SYSREG_CNTV_CVAL_EL0 SYSREG(3, 3, 14, 3, 2)
> #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
>
> #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)
> @@ -502,6 +505,7 @@ int hvf_arch_get_registers(CPUState *cpu)
> uint64_t val;
> hv_simd_fp_uchar16_t fpval;
> int i, n;
> + bool b;
>
> for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
> ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val);
> @@ -631,6 +635,16 @@ int hvf_arch_get_registers(CPUState *cpu)
>
> aarch64_restore_sp(env, arm_current_el(env));
>
> + ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &val);
> + assert_hvf_ok(ret);
> + b = hvf_sysreg_write_cp(cpu, "VTimer", SYSREG_CNTV_CVAL_EL0, val);
> + assert(b);
> +
> + ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &val);
> + assert_hvf_ok(ret);
> + b = hvf_sysreg_write_cp(cpu, "VTimer", SYSREG_CNTV_CTL_EL0, val);
> + assert(b);
> +
> return 0;
> }
>
> @@ -642,6 +656,7 @@ int hvf_arch_put_registers(CPUState *cpu)
> uint64_t val;
> hv_simd_fp_uchar16_t fpval;
> int i, n;
> + bool b;
>
> for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
> val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
> @@ -756,6 +771,16 @@ int hvf_arch_put_registers(CPUState *cpu)
> ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset);
> assert_hvf_ok(ret);
>
> + b = hvf_sysreg_read_cp(cpu, "VTimer", SYSREG_CNTV_CVAL_EL0, &val);
> + assert(b);
> + ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, val);
> + assert_hvf_ok(ret);
> +
> + b = hvf_sysreg_read_cp(cpu, "VTimer", SYSREG_CNTV_CTL_EL0, &val);
> + assert(b);
> + ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, val);
> + assert_hvf_ok(ret);
> +
> return 0;
> }
My Linux guest has been unable to start since this patch. I tested it on
M1 (macOS Tahoe 26.2). Not sure if this can be reproduced on your side.
Thanks,
Zenghui
next prev parent reply other threads:[~2026-02-12 15:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-18 21:59 [PATCH v5 0/2] accel/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0 Philippe Mathieu-Daudé
2026-01-18 21:59 ` [PATCH v5 1/2] target/arm/hvf: Move hvf_sysreg_[read, write]_cp() functions around Philippe Mathieu-Daudé
2026-01-18 21:59 ` [PATCH v5 2/2] target/arm/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0 Philippe Mathieu-Daudé
2026-02-12 15:05 ` Zenghui Yu [this message]
2026-02-17 21:36 ` Philippe Mathieu-Daudé
2026-02-15 10:15 ` Mohamed Mediouni
2026-02-17 21:37 ` Philippe Mathieu-Daudé
2026-02-23 13:47 ` Lucas Kornicki
2026-03-02 12:18 ` Zenghui Yu
2026-01-18 23:26 ` [PATCH v5 0/2] accel/hvf: " Richard Henderson
2026-01-19 3:12 ` Akihiko Odaki
2026-01-26 15:57 ` Peter Maydell
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