From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35210CD3424 for ; Fri, 1 May 2026 12:38:51 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4200A84605; Fri, 1 May 2026 14:38:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="BM8BLKzi"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 98EFF80F0E; Fri, 1 May 2026 12:10:52 +0200 (CEST) Received: from tor.source.kernel.org (tor.source.kernel.org [IPv6:2600:3c04:e001:324:0:1991:8:25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D5A6E803C6 for ; Fri, 1 May 2026 12:10:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@kernel.org Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 574846011F; Fri, 1 May 2026 10:10:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4E7E2C2BCB4; Fri, 1 May 2026 10:10:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777630247; bh=r5NwoooOWk07WxpAbe94TI0no/Vorw4aKZrg8UCaTeY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=BM8BLKzi7FncURHPAORSGmOr5bQKpqIgmHurRiQ26NqvWKkF+35LelVitGLi1igWu U/C4blSQFGcQTMrDe+hB6ICnOaHmNe0iB69hH6AfyC+ZgOxN6pGQ+SaiJbAaw2Rd6C PrvFkbS6JiDHZmiYkWYYNE5ihSEVwn75dMpUGNPmNpCF+7t1AiPofIs5iymzAA/T9m JdJMmZTsvxBdbDpJe0HAXiIe451ywWMsfsMZD8Vf+vT/HAmHLFO2zU+lqhpZw+kpEO u0h0u9C2pY0VGGvRp2JJdE6eSsqGCoJmZN9+DjwpIhLDtxHLUkzLeU3ADpVEQFSKQQ rowsG7X212FDw== Date: Fri, 1 May 2026 15:40:31 +0530 From: Sumit Garg To: michael.srba@seznam.cz Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io, Tom Rini , Ilias Apalodimas , Simon Glass , Sughosh Ganu , Anshul Dalal , Peng Fan , Mattijs Korpershoek , Quentin Schulz , Heinrich Schuchardt , Andrew Davis , Hrushikesh Salunke , Dario Binacchi , Ye Li , Andre Przywara , Alif Zakuan Yuslaimi , Leo Yu-Chi Liang , Andrew Goodbody , Dhruva Gole , Kaustabh Chakraborty , Jerome Forissier , Heiko Schocher , Marek Vasut , Lukasz Majewski , Mateusz Kulikowski , Dinesh Maniyam , Neil Armstrong , Patrice Chotard , Patrick Delaunay , Michal Simek , Yao Zi , Peter Korsgaard , Rayagonda Kokatanur , Casey Connolly , Tingting Meng , Tien Fong Chee , Alice Guo , George Chan , Balaji Selvanathan , Alexey Charkov , Ronald Wahl , Michael Trimarchi Subject: Re: [PATCH v4 04/11] mach-snapdragon: boot0.h: split out msm8916_boot0.h Message-ID: References: <20260426-qcom_spl-v4-0-8cf4133ff883@seznam.cz> <20260426-qcom_spl-v4-4-8cf4133ff883@seznam.cz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260426-qcom_spl-v4-4-8cf4133ff883@seznam.cz> X-Mailman-Approved-At: Fri, 01 May 2026 14:38:15 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Sun, Apr 26, 2026 at 01:26:06AM +0200, michael.srba@seznam.cz wrote: > From: Michael Srba > > Prepare for supporting alternative boot0.h per-SoC by splitting out > the existing msm8916-specific code. > > Signed-off-by: Michael Srba > Reviewed-by: Simon Glass > --- > arch/arm/mach-snapdragon/include/mach/boot0.h | 57 ++-------------------- > .../mach-snapdragon/include/mach/msm8916_boot0.h | 54 ++++++++++++++++++++ > 2 files changed, 59 insertions(+), 52 deletions(-) > > diff --git a/arch/arm/mach-snapdragon/include/mach/boot0.h b/arch/arm/mach-snapdragon/include/mach/boot0.h > index 953cccad790..44a764788de 100644 > --- a/arch/arm/mach-snapdragon/include/mach/boot0.h > +++ b/arch/arm/mach-snapdragon/include/mach/boot0.h > @@ -1,54 +1,7 @@ > /* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Workaround for "PSCI bug" on DragonBoard 410c > - * Copyright (C) 2021 Stephan Gerhold > - * > - * Syscall parameters taken from Qualcomm's LK fork (scm.h): > - * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. > - * > - * The PSCI implementation in the TrustZone/tz firmware on DragonBoard 410c has > - * a bug that starts all other CPU cores in 32-bit mode unless the TZ syscall > - * that switches from 32-bit to 64-bit mode is executed at least once. > - * > - * Normally this happens inside Qualcomm's LK bootloader which runs in 32-bit > - * mode and uses the TZ syscall to boot a kernel in 64-bit mode. However, if > - * U-Boot is installed to the "aboot" partition (replacing LK) the switch to > - * 64-bit mode never happens since U-Boot is already running in 64-bit mode. > - * > - * A workaround for this "PSCI bug" is to execute the TZ syscall when entering > - * U-Boot. That way PSCI is made aware of the 64-bit switch and starts all other > - * CPU cores in 64-bit mode as well. > - */ > -#include > - > -#define ARM_SMCCC_SIP32_FAST_CALL \ > - ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32, ARM_SMCCC_OWNER_SIP, 0) > - > - /* > - * U-Boot might be started in EL2 or EL3 with custom firmware. > - * In that case, we assume that the workaround is not necessary or is > - * handled already by the alternative firmware. Using the syscall in EL2 > - * would demote U-Boot to EL1; in EL3 it would probably just crash. > - */ > - mrs x0, CurrentEL > - cmp x0, #(1 << 2) /* EL1 */ > - bne reset > - > - /* Prepare TZ syscall parameters */ > - mov x0, #ARM_SMCCC_SIP32_FAST_CALL > - movk x0, #0x10f /* SCM_SVC_MILESTONE_CMD_ID */ > - mov x1, #0x12 /* MAKE_SCM_ARGS(0x2, SMC_PARAM_TYPE_BUFFER_READ) */ > - adr x2, el1_system_param > - mov x3, el1_system_param_end - el1_system_param > - > - /* Switch PSCI to 64-bit mode. Resets CPU and returns at el1_elr */ > - smc #0 > - > - /* Something went wrong, perhaps PSCI is already in 64-bit mode? */ > +#if defined(CONFIG_SPL_BUILD) Rather than this SPL build check... > b reset > - > - .align 3 > -el1_system_param: > - .quad 0, 0, 0, 0, 0, 0, 0, 0, 0 /* el1_x0-x8 */ > - .quad reset /* el1_elr */ > -el1_system_param_end: > +#else > +/* currently only db410c enables boot0.h in u-boot proper */ > +#include "msm8916_boot0.h" ...add a special Kconfig option for msm8916 too like follows: BOOT0_MSM8916_PSCI_WORKAROUND and enable it for db410c special defconfig. -Sumit > +#endif > diff --git a/arch/arm/mach-snapdragon/include/mach/msm8916_boot0.h b/arch/arm/mach-snapdragon/include/mach/msm8916_boot0.h > new file mode 100644 > index 00000000000..953cccad790 > --- /dev/null > +++ b/arch/arm/mach-snapdragon/include/mach/msm8916_boot0.h > @@ -0,0 +1,54 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Workaround for "PSCI bug" on DragonBoard 410c > + * Copyright (C) 2021 Stephan Gerhold > + * > + * Syscall parameters taken from Qualcomm's LK fork (scm.h): > + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. > + * > + * The PSCI implementation in the TrustZone/tz firmware on DragonBoard 410c has > + * a bug that starts all other CPU cores in 32-bit mode unless the TZ syscall > + * that switches from 32-bit to 64-bit mode is executed at least once. > + * > + * Normally this happens inside Qualcomm's LK bootloader which runs in 32-bit > + * mode and uses the TZ syscall to boot a kernel in 64-bit mode. However, if > + * U-Boot is installed to the "aboot" partition (replacing LK) the switch to > + * 64-bit mode never happens since U-Boot is already running in 64-bit mode. > + * > + * A workaround for this "PSCI bug" is to execute the TZ syscall when entering > + * U-Boot. That way PSCI is made aware of the 64-bit switch and starts all other > + * CPU cores in 64-bit mode as well. > + */ > +#include > + > +#define ARM_SMCCC_SIP32_FAST_CALL \ > + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32, ARM_SMCCC_OWNER_SIP, 0) > + > + /* > + * U-Boot might be started in EL2 or EL3 with custom firmware. > + * In that case, we assume that the workaround is not necessary or is > + * handled already by the alternative firmware. Using the syscall in EL2 > + * would demote U-Boot to EL1; in EL3 it would probably just crash. > + */ > + mrs x0, CurrentEL > + cmp x0, #(1 << 2) /* EL1 */ > + bne reset > + > + /* Prepare TZ syscall parameters */ > + mov x0, #ARM_SMCCC_SIP32_FAST_CALL > + movk x0, #0x10f /* SCM_SVC_MILESTONE_CMD_ID */ > + mov x1, #0x12 /* MAKE_SCM_ARGS(0x2, SMC_PARAM_TYPE_BUFFER_READ) */ > + adr x2, el1_system_param > + mov x3, el1_system_param_end - el1_system_param > + > + /* Switch PSCI to 64-bit mode. Resets CPU and returns at el1_elr */ > + smc #0 > + > + /* Something went wrong, perhaps PSCI is already in 64-bit mode? */ > + b reset > + > + .align 3 > +el1_system_param: > + .quad 0, 0, 0, 0, 0, 0, 0, 0, 0 /* el1_x0-x8 */ > + .quad reset /* el1_elr */ > +el1_system_param_end: > > -- > 2.53.0 >