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R. Silva" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ze Huang , Alex Elder , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Yixun Lan , Longbin Li Subject: Re: [PATCH 1/2] dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy support Message-ID: References: <20260430022843.1090138-1-inochiama@gmail.com> <20260430022843.1090138-2-inochiama@gmail.com> <20260504-logical-nice-python-1e1f43@quoll> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260504-logical-nice-python-1e1f43@quoll> On Mon, May 04, 2026 at 11:54:11AM +0200, Krzysztof Kozlowski wrote: > On Thu, Apr 30, 2026 at 10:28:40AM +0800, Inochi Amaoto wrote: > > +properties: > > + compatible: > > + const: spacemit,k3-comb-phy > > + > > + reg: > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 2 > > + description: > > + The first one is phy id, the second one is phy type. > > You could mention here the defines representing supported phy types. > OK. > > + > > + spacemit,apb-spare: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to APB SPARE system controller interface, used for > > + PHY calibration. > > + > > + spacemit,apmu: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + - items: > > + - description: phandle of APMU syscon > > + - description: configuration of the PHY lanes > > + description: | > > + Phandle to control PHY mux configuration. The configuration > > + is described as follows: > > + bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode > > + bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode > > + bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode > > + bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode > > + bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode > > I assume this device k3-comb-phy handles phys for PCIe A, B, C and D? > In fact it handles phys for PCIe A-E. The mux for the phy of PCIe E (the id is 5) is controlled by bit 4. If the comb PHY is in shared mode, the PCIe E always got one lane. I think it is good to add a public link for this configuration, but Spacemit has no opened any document for this publicly.... > > + > > + The bit[3:0] is only valid when bit 4 is 1. > > + > > +required: > > + - compatible > > reg required. > It is fine for me > > + - "#phy-cells" > > + - spacemit,apb-spare > > + - spacemit,apmu > > + > > +additionalProperties: false > > Best regards, > Krzysztof > Regards, Inochi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5A6ECD342C for ; Mon, 4 May 2026 10:21:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 04 May 2026 03:21:14 -0700 (PDT) Date: Mon, 4 May 2026 18:20:59 +0800 From: Inochi Amaoto To: Krzysztof Kozlowski , Inochi Amaoto Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Kees Cook , "Gustavo A. R. Silva" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ze Huang , Alex Elder , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Yixun Lan , Longbin Li Subject: Re: [PATCH 1/2] dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy support Message-ID: References: <20260430022843.1090138-1-inochiama@gmail.com> <20260430022843.1090138-2-inochiama@gmail.com> <20260504-logical-nice-python-1e1f43@quoll> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260504-logical-nice-python-1e1f43@quoll> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260504_032118_973091_49C0341C X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Mon, May 04, 2026 at 11:54:11AM +0200, Krzysztof Kozlowski wrote: > On Thu, Apr 30, 2026 at 10:28:40AM +0800, Inochi Amaoto wrote: > > +properties: > > + compatible: > > + const: spacemit,k3-comb-phy > > + > > + reg: > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 2 > > + description: > > + The first one is phy id, the second one is phy type. > > You could mention here the defines representing supported phy types. > OK. > > + > > + spacemit,apb-spare: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to APB SPARE system controller interface, used for > > + PHY calibration. > > + > > + spacemit,apmu: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + - items: > > + - description: phandle of APMU syscon > > + - description: configuration of the PHY lanes > > + description: | > > + Phandle to control PHY mux configuration. The configuration > > + is described as follows: > > + bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode > > + bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode > > + bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode > > + bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode > > + bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode > > I assume this device k3-comb-phy handles phys for PCIe A, B, C and D? > In fact it handles phys for PCIe A-E. The mux for the phy of PCIe E (the id is 5) is controlled by bit 4. If the comb PHY is in shared mode, the PCIe E always got one lane. I think it is good to add a public link for this configuration, but Spacemit has no opened any document for this publicly.... > > + > > + The bit[3:0] is only valid when bit 4 is 1. > > + > > +required: > > + - compatible > > reg required. > It is fine for me > > + - "#phy-cells" > > + - spacemit,apb-spare > > + - spacemit,apmu > > + > > +additionalProperties: false > > Best regards, > Krzysztof > Regards, Inochi -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A211FCD342C for ; Mon, 4 May 2026 10:21:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; 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Mon, 04 May 2026 03:21:15 -0700 (PDT) Received: from localhost ([2001:19f0:8001:1b2d:5400:5ff:fefa:a95d]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8357c4f4530sm4335636b3a.9.2026.05.04.03.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 03:21:14 -0700 (PDT) Date: Mon, 4 May 2026 18:20:59 +0800 From: Inochi Amaoto To: Krzysztof Kozlowski , Inochi Amaoto Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Kees Cook , "Gustavo A. R. Silva" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ze Huang , Alex Elder , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Yixun Lan , Longbin Li Subject: Re: [PATCH 1/2] dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy support Message-ID: References: <20260430022843.1090138-1-inochiama@gmail.com> <20260430022843.1090138-2-inochiama@gmail.com> <20260504-logical-nice-python-1e1f43@quoll> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260504-logical-nice-python-1e1f43@quoll> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260504_032118_982064_8286351D X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, May 04, 2026 at 11:54:11AM +0200, Krzysztof Kozlowski wrote: > On Thu, Apr 30, 2026 at 10:28:40AM +0800, Inochi Amaoto wrote: > > +properties: > > + compatible: > > + const: spacemit,k3-comb-phy > > + > > + reg: > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 2 > > + description: > > + The first one is phy id, the second one is phy type. > > You could mention here the defines representing supported phy types. > OK. > > + > > + spacemit,apb-spare: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to APB SPARE system controller interface, used for > > + PHY calibration. > > + > > + spacemit,apmu: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + - items: > > + - description: phandle of APMU syscon > > + - description: configuration of the PHY lanes > > + description: | > > + Phandle to control PHY mux configuration. The configuration > > + is described as follows: > > + bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode > > + bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode > > + bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode > > + bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode > > + bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode > > I assume this device k3-comb-phy handles phys for PCIe A, B, C and D? > In fact it handles phys for PCIe A-E. The mux for the phy of PCIe E (the id is 5) is controlled by bit 4. If the comb PHY is in shared mode, the PCIe E always got one lane. I think it is good to add a public link for this configuration, but Spacemit has no opened any document for this publicly.... > > + > > + The bit[3:0] is only valid when bit 4 is 1. > > + > > +required: > > + - compatible > > reg required. > It is fine for me > > + - "#phy-cells" > > + - spacemit,apb-spare > > + - spacemit,apmu > > + > > +additionalProperties: false > > Best regards, > Krzysztof > Regards, Inochi _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv