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Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7583 Received-SPF: permerror client-ip=2a01:111:f403:c107::1; envelope-from=nicolinc@nvidia.com; helo=PH8PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.444, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Wed, Apr 15, 2026 at 11:55:35AM +0100, Shameer Kolothum wrote: LGTM. Some nits: > diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h > index fa0aa3ab04..965670066d 100644 > --- a/hw/arm/tegra241-cmdqv.h > +++ b/hw/arm/tegra241-cmdqv.h > @@ -10,10 +10,14 @@ > #ifndef HW_ARM_TEGRA241_CMDQV_H > #define HW_ARM_TEGRA241_CMDQV_H > > +#include "hw/core/registerfields.h" > + > #define CMDQV_VER 1 > #define CMDQV_NUM_CMDQ_LOG2 1 > #define CMDQV_NUM_SID_PER_VI_LOG2 4 > > +#define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2) Maybe add: #define TEGRA241_CMDQV_MAX_NUM_SID (1U << CMDQV_NUM_SID_PER_VI_LOG2) > /* > * Tegra241 CMDQV MMIO layout (64KB pages) > * > @@ -31,8 +35,131 @@ typedef struct Tegra241CMDQV { > MemoryRegion mmio_cmdqv; > qemu_irq irq; > IOMMUFDVeventq *veventq; > + > + /* Register Cache */ > + uint32_t config; > + uint32_t param; > + uint32_t status; > + uint32_t vi_err_map[2]; > + uint32_t vi_int_mask[2]; > + uint32_t cmdq_err_map[4]; > + uint32_t cmdq_alloc_map[TEGRA241_CMDQV_MAX_CMDQ]; > + uint32_t vintf_config; > + uint32_t vintf_status; [...] > + uint32_t vintf_sid_match[16]; > + uint32_t vintf_sid_replace[16]; Then s/16/TEGRA241_CMDQV_MAX_NUM_SID > +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_(i) \ > + REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \ > + FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \ > + FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \ > + FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6) > + > +SMMU_CMDQV_CMDQ_ALLOC_MAP_(0) > +SMMU_CMDQV_CMDQ_ALLOC_MAP_(1) > + > + Can drop the extra line. > static void tegra241_cmdqv_free_viommu(SMMUv3State *s) > @@ -84,8 +235,8 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) > } > > static const MemoryRegionOps mmio_cmdqv_ops = { > - .read = tegra241_cmdqv_read, > - .write = tegra241_cmdqv_write, > + .read = tegra241_cmdqv_read_mmio, > + .write = tegra241_cmdqv_write_mmio, > .endianness = DEVICE_LITTLE_ENDIAN, This could squash to PATCH-11. Nicolin