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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7615 Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=nicolinc@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.444, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Wed, Apr 15, 2026 at 11:55:40AM +0100, Shameer Kolothum wrote: > +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, > + Error **errp) > +{ > + SMMUv3AccelState *accel = cmdqv->s_accel; > + uint64_t base_mask = (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK | > + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32; > + uint64_t addr = cmdqv->vcmdq_base[index] & base_mask; > + uint64_t log2 = cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_MASK; > + uint64_t size = 1ULL << (log2 + 4); > + IOMMUFDViommu *viommu = accel->viommu; > + IOMMUFDHWqueue *hw_queue; > + uint32_t hw_queue_id; > + > + /* Ignore any invalid address. This may come as part of reset etc. */ > + if (!address_space_is_ram(&address_space_memory, addr) || > + !address_space_is_ram(&address_space_memory, addr + size - 1)) { Overflow prevention: size - 1 + addr > + if (!tegra241_cmdq_enabled(cmdqv) || !tegra241_vintf_enabled(cmdqv)) { > + return true; > + } It's good to have these two checks. But if vcmdq setup is skipped for vintf=disabled, we need to call this setup() again upon vintf gets enabled? Also, do we fence against unassigned vcmdq? Corner case is that a guest might write base address registers via direct (global) MMIO space. > @@ -363,7 +427,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, > */ > index = (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; > tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE, > - index, value, size); > + index, value, size, &local_err); > break; > case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: > /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above */ > @@ -373,7 +437,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, > /* Same decode logic as VCMDQ Page0 case above */ > index = (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; > tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE, > - index, value, size); > + index, value, size, &local_err); Should these two be squashed into an earlier patch? Nicolin