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Mon, 4 May 2026 13:23:09 -0700 Date: Mon, 4 May 2026 13:23:06 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , David Matlack Subject: Re: [PATCH rc v2] iommu/arm-smmu-v3: Fix inconsistent ATS state tracking Message-ID: References: <20260504163842.2692314-1-praan@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C9:EE_|DS7PR12MB5814:EE_ X-MS-Office365-Filtering-Correlation-Id: 47403dc1-486c-434f-38f1-08deaa1b040b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|7416014|376014|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Femqzo7TzOslc2p4eszEiJo/zCo/yOKMuVQ1RTGU5Ft98RWuTBfXdAEg2zxNhhxftAWzGaFBO5cL1GGt8vBkQTE+LGigNgAiMmU6s9BRHKYJ6NG3kqNHPKzFrpfVjyc7isQH6qSG0WEpZcWQZ2ibDAJWH1SGe75/NGocTm8ubtLqVb3cMOkLiUfukQPCMUi4OD3e9MYPwYyzoFbfIR/MQT/RfTaJMjJQKg65xtLg5zQjytoaADpJ893mhdosaDGgtLCo/1DItIRaHvcJM2cd2ef+yUzh0WjZFfd3pMBMmBk8etdMCIvn4+Pdaf8oJel1Opepn9Ck6Jr1WImMZzkUo/xqBpDv9FItjq9YJodn7tL+or7WhkImHki4ZZ0ybKj4WitOUpPjX6+UYOEMykDifOWTgGDsyN28pGw/S0qgyrlSwl2C4B6g/tggzMjkRmW4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2026 20:23:34.1220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47403dc1-486c-434f-38f1-08deaa1b040b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5814 On Mon, May 04, 2026 at 07:33:07PM +0000, Pranjal Shrivastava wrote: > On Mon, May 04, 2026 at 11:01:42AM -0700, Nicolin Chen wrote: > > On Mon, May 04, 2026 at 04:38:42PM +0000, Pranjal Shrivastava wrote: > > I am thinking, maybe the call sites of pci_enable/disable_ats() can > > check to_pci_dev(dev)->ats_enabled instead of master->ats_enabled? > > > > Then, we keep master->ats_enabled as-is, so detach() can revert the > > nr_ats_masters and ATS invalidation entry in domain->invs. > > My suggestion in that case would be to update arm_smmu_ats_supported to > check if the client is a VF and check if it's PF enables ATS: > > static bool arm_smmu_ats_supported(struct arm_smmu_master *master) > { > struct device *dev = master->dev; > struct pci_dev *pdev; > > if (!dev_is_pci(dev)) > return false; > > pdev = to_pci_dev(dev); > if (!pci_ats_supported(pdev)) > return false; > > /* > * If this is a VF, ATS only works if the PF has already enabled it > * with a valid STU. > */ > if (pdev->is_virtfn && !pci_physfn(pdev)->ats_enabled) > return false; > > return true; > } I think that's okay to address the issue for now. But it assumes that pci_enable_ats() will never change so it won't fail for any other reason. > and then in attach_prepare we can add the ats check for safety: > > if (!state->ats_enabled && master->ats_enabled) { > pci_disable_ats(to_pci_dev(master->dev)); > > + if (pdev->ats_enabled) > + pci_disable_ats(to_pci_dev(master->dev)); master->ats_enabled is redundant if we check pdev->ats_enabled. If we add a gate here, should add to pci_enable_ats() too? Nicolin