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Mon, 4 May 2026 13:51:34 -0700 Date: Mon, 4 May 2026 13:51:32 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , David Matlack Subject: Re: [PATCH rc v2] iommu/arm-smmu-v3: Fix inconsistent ATS state tracking Message-ID: References: <20260504163842.2692314-1-praan@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|DS7PR12MB5983:EE_ X-MS-Office365-Filtering-Correlation-Id: b90a69e0-ad0c-4654-5774-08deaa1f014f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700016|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: fuNfoeVfSOjCVE30sxyixgwJH72IqDd24taX3wdU4ewpDDxMOF+cKyPciHX3ITVf5HC5yin3ljyQJaXheLe9wiVMpmhorwHJPayJnRKkm6oikSLVRGKjzT42HmEF8c7rReHf4yz/5/L7+exIEC2LwmCxZJ5zThKUe5zicr5PEZB9NgL9zryDD0So1796VraZL4Rr1MAfiCoRoLrGKlvDuy8Tf6cJ553BUso4NxtUQDXaVyXbTkdLAAcmY3b8nmT1zX+RUhU515qXPJFFikbZCIFqUZHXubG/omc3KvNOHvRAC/KMxZ4nbxuhD4BjVJsPAK3HZgaUmW+5P/eXn2mpS4umValEYBAIvZVwEc16ikC1W/aZlXVq3hhRVXlPDGDLMpIj4WfB6flgEnnF7HpSluk0eH+ZXg7Qhem8MI7K6G0m8E4yHqiSBXuPHjBtHfhQt5Rcye5UjP6R7J9iTvtn7x3FxHLwR17fa+/ahBllSQnl35zEvVhQgdmiv8phyf8in+yxE3QYZRV5QRdrEizVP48XPvWD6KYr5ZgOHajWinm495fKZQAB0+qO2Lvja0vOoDZPMjF2rWeQe6No+BYQT1+2KSSmwRWEhC0/08Hel/pfQt46YACTAF1lvWMpGLOrdRLk2cMrshmotf1KWdEdYLX9Oy0yMmb4HkkffGM4YLIA8WVGvv5EkinJzE+BPjROhBUuH/PY6XGx8EDYQzbxCQwdNB0WtcKb57dZqSXkuL8= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700016)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yG09BLdkoQe4NuHT2cSKO3ZtGRhkecAxYVZI6kf5hf9dfVh9HwoHhvnfKY0jYs3d57uwVWGMM3SwOdXAid3ReAgy6LtdNRJrz/0uoDbFQuqFYSDpn15RkGfpoK3eerWc3VN2D5vT5VHhndLimlAHXJEsf5R6RTbyPSgcSPfzSBvfm03KIUCBwGXAutFdNAU6IJ0k1WHLlniDMsYRG6V+ZNP/e1ItWoboBLI3QzNVq0hSv1fQ/8GRmlXwkvYDwaBghBSdvk+ozJdpS0ZSd1wirV6xUO4wDUCPCiqiorgVXhgLIjBzVfqEF1vadGLGa8Pr+IKn06uk6j+yZiMWjhEBMjZBONjXOZ38/VDnpKX+DXOcOLDdFeXYiR3+9+3BxXVs7gJUtOEU4u15BQu7hnXtW++LigQYqXFyujY0xhPwtcQ/kn34LanfxMd9CX6m3xPC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2026 20:52:07.4391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b90a69e0-ad0c-4654-5774-08deaa1f014f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5983 On Mon, May 04, 2026 at 08:29:29PM +0000, Pranjal Shrivastava wrote: > On Mon, May 04, 2026 at 01:23:06PM -0700, Nicolin Chen wrote: > > On Mon, May 04, 2026 at 07:33:07PM +0000, Pranjal Shrivastava wrote: > > > On Mon, May 04, 2026 at 11:01:42AM -0700, Nicolin Chen wrote: > > > > On Mon, May 04, 2026 at 04:38:42PM +0000, Pranjal Shrivastava wrote: > > > > I am thinking, maybe the call sites of pci_enable/disable_ats() can > > > > check to_pci_dev(dev)->ats_enabled instead of master->ats_enabled? > > > > > > > > Then, we keep master->ats_enabled as-is, so detach() can revert the > > > > nr_ats_masters and ATS invalidation entry in domain->invs. > > > > > > My suggestion in that case would be to update arm_smmu_ats_supported to > > > check if the client is a VF and check if it's PF enables ATS: > > > > > > static bool arm_smmu_ats_supported(struct arm_smmu_master *master) > > > { > > > struct device *dev = master->dev; > > > struct pci_dev *pdev; > > > > > > if (!dev_is_pci(dev)) > > > return false; > > > > > > pdev = to_pci_dev(dev); > > > if (!pci_ats_supported(pdev)) > > > return false; > > > > > > /* > > > * If this is a VF, ATS only works if the PF has already enabled it > > > * with a valid STU. > > > */ > > > if (pdev->is_virtfn && !pci_physfn(pdev)->ats_enabled) > > > return false; > > > > > > return true; > > > } > > > > I think that's okay to address the issue for now. But it assumes > > that pci_enable_ats() will never change so it won't fail for any > > other reason. > > > > Hmm.. in that case, could we factor out the > > if (dev->is_virtfn) { > pdev = pci_physfn(dev); > if (pdev->ats_stu != ps) > return -EINVAL; > } > > part into a helper and export it? I think iommu drivers could use it? I think having two identical checks in the same attach_dev() path isn't that necessary.. Also, stu is __ffs(smmu->pgsize_bitmap). stu should match if both are set. The implication is still that if pf is ats_enabled. I prefer your previous version. Nicolin