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Mon, 04 May 2026 18:38:56 -0700 (PDT) Received: from localhost ([124.158.97.178]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-839679c9293sm194413b3a.33.2026.05.04.18.38.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 18:38:56 -0700 (PDT) Date: Tue, 5 May 2026 11:38:52 +1000 From: Nicholas Piggin To: Alistair Francis Cc: Joel Stanley , Alistair Francis , Daniel Henrique Barboza , Chao Liu , Michael Ellerman , Joel Stanley , Anirudh Srinivasan , Portia Stephens , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v4 10/13] hw/riscv/atlantis: Add PCIe controller Message-ID: References: <20260425131721.932250-1-joel@jms.id.au> <20260425131721.932250-11-joel@jms.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=npiggin@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Apr 30, 2026 at 10:04:16AM +1000, Alistair Francis wrote: > On Sat, Apr 25, 2026 at 11:21 PM Joel Stanley wrote: > > > > From: Nicholas Piggin > > > > Atlantis has 3 DesignWare PCIe host controllers, however the boot firmware > > has not been tested with the QEMU DesignWare model so a generic ECAM > > controller is used for the interim. The system bus aperture and PCIe IO > > I don't follow. > > The actual hardware has a different PCIe controller? This is user > visible so you can't easily change it once it's merged. Generally user > visible changes go through a deprecation process, we have some > exceptions for soft cores which change all the time. But ideally this > should model the hardware from the start. > > Also if it isn't that should be noted in the board documentation. Yeah, this was me punting on doing the designware host to get some IOMMU modeling and driver code tested. And generally being easier to test other things if we have PCI up. I hadn't really considered the stability / deprecation issue with upstreaming it. > A quick grep shows support for a DesignWare PCIe Host, why not use that? We should be, I'll take another look at it. We could drop this and the functional test that uses disk, for now. Thanks, Nick