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Mon, 04 May 2026 23:01:44 -0700 (PDT) Received: from localhost ([124.158.97.178]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364bdf2aa41sm22104297a91.4.2026.05.04.23.01.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 23:01:43 -0700 (PDT) Date: Tue, 5 May 2026 16:01:40 +1000 From: Nicholas Piggin To: Alistair Francis Cc: Joel Stanley , Alistair Francis , Daniel Henrique Barboza , Chao Liu , Michael Ellerman , Joel Stanley , Anirudh Srinivasan , Portia Stephens , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH v4 09/13] hw/riscv: Add Tenstorrent Atlantis machine Message-ID: References: <20260425131721.932250-1-joel@jms.id.au> <20260425131721.932250-10-joel@jms.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, May 05, 2026 at 02:36:23PM +1000, Alistair Francis wrote: > On Tue, May 5, 2026 at 12:00 PM Nicholas Piggin wrote: > > > > On Thu, Apr 30, 2026 at 09:57:34AM +1000, Alistair Francis wrote: > > > On Sat, Apr 25, 2026 at 11:20 PM Joel Stanley wrote: > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > > index e1942a86eba5..635a380945fd 100644 > > > > --- a/MAINTAINERS > > > > +++ b/MAINTAINERS > > > > @@ -1760,6 +1760,17 @@ F: hw/*/*sifive*.c > > > > F: include/hw/*/*sifive*.h > > > > F: tests/functional/test_riscv64_sifive_u.py > > > > > > > > +Tenstorrent Machines > > > > +M: Joel Stanley > > > > +R: Nicholas Piggin > > > > +R: Michael Ellerman > > > > +L: qemu-riscv@nongnu.org > > > > +S: Supported > > > > +F: docs/system/riscv/tt_*.rst > > > > +F: hw/riscv/tt_*.c > > > > +F: hw/riscv/aia.[ch] > > > > > > AIA? > > > > Oh it must be because checkpatch complained about patch 5. > > > > It is covered by RISC-V TCG CPUs though, so no change needed to > > MAINTAINERS for AIA AFAIKS? > > If it's already covered then that should be fine. Also, if you are > covering it, MAINTAINERS should be updated with patch 5 and not here Agree on both counts. I think it was in the wrong patch, but also unnecessary. I've just dropped it. Thanks, Nick