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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6167 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=nicolinc@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.443, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Tue, May 05, 2026 at 08:13:40AM -0700, Shameer Kolothum Thodi wrote: > > From: Nicolin Chen > > On Wed, Apr 15, 2026 at 11:55:41AM +0100, Shameer Kolothum wrote: > > > The pre-to-post-alloc transition is triggered by the BASE register > > > write that initiates IOMMU_HW_QUEUE_ALLOC. No cache-to-hardware > > > synchronisation is needed at transition time. The hardware mandated > > > init sequence requires BASE to be written first; PROD_INDX, CONS_INDX > > > and CONFIG.CMDQ_EN are programmed only after BASE and are therefore > > always post-alloc. > > > > > > Any pre-alloc writes to those registers update only the register > > > cache, which is discarded at the transition. > > > > Is "discard" the correct action? > > > > Guest OS might expect HW (VM) to retain what it writes to those > > page0 registers? > > As explained above, I reached that conclusion based on spec p.174/175: > > Under "Enabling the Virtual CMDQ" it specifies the init order as below: > > - Program the VIRT_CMDQ_BASE > - Init the PROD_INDX/ CONS_INDX to 0 or a consistent value > - Program the VIRT_CMDQ_CONFIG to enable the CMDQ > > Since we set up the HW QUEUE on BASE write, a spec compliant guest is > expected to program the Page0 registers as above after that, and we pass > those writes directly to the VINTF Page0. There are no GERRORN writes > before HW queue setup either. I don't think we can make an assumption that guest would follow what spec suggests. Could this be a case: - Write the PROD_INDX/ CONS_INDX with a consistent value (0xf) - Program the VIRT_CMDQ_BASE - Read the PROD_INDX/CONS_INDX, expecting 0xf - Write the PROD_INDX/ CONS_INDX with 0x0 - Program the VIRT_CMDQ_CONFIG to enable the CMDQ ? Nicolin