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[124.158.97.178]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ba7ca24a62sm12248025ad.75.2026.05.05.22.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 22:58:29 -0700 (PDT) Date: Wed, 6 May 2026 15:58:25 +1000 From: Nicholas Piggin To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Alistair Francis , Joel Stanley , Alistair Francis , Daniel Henrique Barboza , Chao Liu , Chris Rauer , Michael Ellerman , Joel Stanley , Anirudh Srinivasan , Portia Stephens , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Hao Wu Subject: Re: [PATCH v4 01/13] hw/i2c: Add designware i2c controller Message-ID: References: <20260425131721.932250-1-joel@jms.id.au> <20260425131721.932250-2-joel@jms.id.au> <1476b7df-b8b7-492a-b46c-81d0bf9cb66e@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1476b7df-b8b7-492a-b46c-81d0bf9cb66e@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, May 05, 2026 at 09:36:57AM +0200, Philippe Mathieu-Daudé wrote: > On 5/5/26 08:20, Nicholas Piggin wrote: > > On Thu, Apr 30, 2026 at 01:53:21PM +1000, Alistair Francis wrote: > > > On Sat, Apr 25, 2026 at 11:20 PM Joel Stanley wrote: > > > > > > > > From: Chris Rauer > > > > > > > > In the past this model has been submitted for use with the arm virt > > > > machine, however in this case it will be used by the upcoming > > > > Tenstorrent Atlantis RISC-V machine. > > > > > > > > This is a re-submission of the model with Chris' permission, with a > > > > light touch of updates to make it build with qemu master. > > > > > > > > Reviewed-by: Hao Wu > > > > Signed-off-by: Chris Rauer > > > > Link: https://lore.kernel.org/qemu-devel/20220110214755.810343-2-venture@google.com > > > > [jms: rebase and minor build fixes for class_init and reset callback] > > > > Signed-off-by: Joel Stanley > > > > --- > > > > > > +#define DW_IC_COMP_PARAM_1_HAS_ENCODED_PARAMS BIT(7) > > > > +#define DW_IC_COMP_PARAM_1_HAS_DMA 0 /* bit 6 - DMA disabled. */ > > > > +#define DW_IC_COMP_PARAM_1_INTR_IO BIT(5) > > > > +#define DW_IC_COMP_PARAM_1_HC_COUNT_VAL 0 /* bit 4 - disabled */ > > > > +#define DW_IC_COMP_PARAM_1_HIGH_SPEED_MODE (BIT(2) | BIT(3)) > > > > +#define DW_IC_COMP_PARAM_1_APB_DATA_WIDTH_32 BIT(1) /* bits 0, 1 */ > > > > +#define DW_IC_COMP_PARAM_1_INIT_VAL \ > > > > + (DW_IC_COMP_PARAM_1_APB_DATA_WIDTH_32 | \ > > > > + DW_IC_COMP_PARAM_1_HIGH_SPEED_MODE | \ > > > > + DW_IC_COMP_PARAM_1_HC_COUNT_VAL | \ > > > > + DW_IC_COMP_PARAM_1_INTR_IO | \ > > > > + DW_IC_COMP_PARAM_1_HAS_DMA | \ > > > > + DW_IC_COMP_PARAM_1_HAS_ENCODED_PARAMS | \ > > > > + ((DESIGNWARE_I2C_RX_FIFO_SIZE - 1) << 8) | \ > > > > + ((DESIGNWARE_I2C_TX_FIFO_SIZE - 1) << 16)) > > > > +#define DW_IC_COMP_VERSION_INIT_VAL 0x3132302a > > > > +#define DW_IC_COMP_TYPE_INIT_VAL 0x44570140 > > > > > > I would prefer these to sue the QEMU register API > > > > That's probably a good idea. It's a lot of churn to change it, but > > I'm having a try. Might do it as a follow on patch. > > Good suggestion but please as a follow up, this patch is already > big enough, is reviewed and tested. I agree... however I implemented it and it is a large amount of chrun which is also not easy to review. Also it breaks migration compatibility. So I don't want to get this patch bogged down but if we agree to take the register API conversion then maybe we should squash before upstreaming? Not sure. I will post the patch as a separate optional addition to the series to begin with. Thanks, Nick