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From: "Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>
To: Magnus Kulke <magnuskulke@linux.microsoft.com>
Cc: qemu-devel@nongnu.org, "Wei Liu" <wei.liu@kernel.org>,
	"Zhao Liu" <zhao1.liu@intel.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Wei Liu" <liuwe@microsoft.com>,
	"Magnus Kulke" <magnuskulke@microsoft.com>,
	"Doru Blânzeanu" <dblanzeanu@microsoft.com>
Subject: Re: [PATCH v6 8/9] target/i386/mshv: use hv-provided [0xD,1+2].EBX
Date: Wed, 6 May 2026 14:14:07 +0300	[thread overview]
Message-ID: <afsif7mIeVDFqhVv@linux.microsoft.com> (raw)
In-Reply-To: <20260416121116.527927-9-magnuskulke@linux.microsoft.com>

On Thu, Apr 16, 2026 at 02:11:15PM +0200, Magnus Kulke wrote:
> We cannot statically set the responses for CPUID[0xD,{1,2}].EBX, b/c
> those are dynamic, dependent on which features the guest enables.
> 
> Hence we mask EBX when registering answers for those subleaves at the
> hypervisor, which will result in the hypervisor providing us answers,
> considering XCR0 and XSS.
> 
> The reported size now reflects the field masks properly (without the
> mask they were 576 and 10728, which is wrong):
> 
> $ cpuid -l 0xd -s 0
> CPU 0:
>    XSAVE features (0xd/0):
>       XCR0 valid bit field mask               = 0x00000000000600e7
>       ...
>       bytes required by fields in XCR0        = 0x00002b00 (11008)
>       bytes required by XSAVE/XRSTOR area     = 0x00002b00 (11008)
> 
> $ cpuid -l 0xd -s 1
> CPU 0:
>    XSAVE features (0xd/1):
>       ...
>       SAVE area size in bytes                     = 0x000029c0 (10688)
>       IA32_XSS lower 32 bits valid bit field mask = 0x00001800
>       IA32_XSS upper 32 bits valid bit field mask = 0x00000000
> 
> Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
> ---
>  target/i386/mshv/mshv-cpu.c | 23 +++++++++++++++++++++--
>  1 file changed, 21 insertions(+), 2 deletions(-)
>

Reviewed-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>


  reply	other threads:[~2026-05-06 11:14 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-16 12:11 [PATCH v6 0/9] Support QEMU cpu models in MSHV accelerator Magnus Kulke
2026-04-16 12:11 ` [PATCH v6 1/9] accel/mshv: use mshv_create_partition_v2 payload Magnus Kulke
2026-04-30  8:43   ` Doru Blânzeanu
2026-04-16 12:11 ` [PATCH v6 2/9] target/i386/mshv: fix cpuid propagation bug Magnus Kulke
2026-04-30  9:05   ` Doru Blânzeanu
2026-04-16 12:11 ` [PATCH v6 3/9] target/i386/mshv: fix various cpuid traversal bugs Magnus Kulke
2026-04-30  9:35   ` Doru Blânzeanu
2026-04-16 12:11 ` [PATCH v6 4/9] target/i386/mshv: change cpuid mask to UINT32_MAX Magnus Kulke
2026-04-30 11:27   ` Doru Blânzeanu
2026-04-16 12:11 ` [PATCH v6 5/9] target/i386/mshv: set cpu model name on -cpu host Magnus Kulke
2026-04-30 11:47   ` Doru Blânzeanu
2026-04-16 12:11 ` [PATCH v6 6/9] target/i386: query mshv accel for supported cpuids Magnus Kulke
2026-05-06 10:41   ` Doru Blânzeanu
2026-04-16 12:11 ` [PATCH v6 7/9] target/i386/mshv: populate xsave area offsets Magnus Kulke
2026-05-06 11:02   ` Doru Blânzeanu
2026-04-16 12:11 ` [PATCH v6 8/9] target/i386/mshv: use hv-provided [0xD,1+2].EBX Magnus Kulke
2026-05-06 11:14   ` Doru Blânzeanu [this message]
2026-04-16 12:11 ` [PATCH v6 9/9] accel/mshv: disable la57 (5lvl paging) Magnus Kulke
2026-05-06 11:24   ` Doru Blânzeanu

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