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Thu, 07 May 2026 10:13:02 -0700 (PDT) Received: from linaro.org ([2a10:d582:31e:0:2cf8:2ace:fcda:630d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4540f92c322sm523732f8f.0.2026.05.07.10.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 10:13:01 -0700 (PDT) Date: Thu, 7 May 2026 18:13:00 +0100 From: Jim MacArthur To: qemu-devel@nongnu.org Cc: Alex Bennee Subject: Re: [PATCH 4/7] tests/tcg: move aarch64 page table setup to c code Message-ID: References: <20260417164328.1009132-1-alex.bennee@linaro.org> <20260417164328.1009132-5-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260417164328.1009132-5-alex.bennee@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=jim.macarthur@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Apr 17, 2026 at 05:43:24PM +0100, Alex Bennée wrote: > If we want more flexibility messing around with page tables lets do it > without having to rely on assembly for it. > > Signed-off-by: Alex Bennée > > --- > AJB > - a result of -O0 does mean each helper ends up with a stack frame > being needed to do the relatively simple mask and shift. I've > experimented with -O1 and trying to manually enable inlining but > couldn't get anything to work. > --- > +#define DESC_AF (1ULL << 10) > +#define DESC_ATTRINDX(i) ((uint64_t)(i) << 2) > +#define DESC_NS (1ULL << 5) > +#define DESC_UXN (1ULL << 53) > +#define DESC_PXN (1ULL << 54) I *think* you have UXN and PXN the wrong way round? See table D8-52; UXN is always 54. It works fine in this case as we always use them together. Otherwise, Reviewed-by: Jim MacArthur