Re: [PATCH v2 3/6] hw/misc: Add Sophgo CV1800B clock controller

[Kuan-Wei Chiu <visitorckw@gmail.com>]

Hi Chao,

On Mon, May 18, 2026 at 06:13:58PM +0800, Chao Liu wrote:
> On Thu, May 14, 2026 at 01:15:25AM +0800, Kuan-Wei Chiu wrote:
> > Add a stub for the CV1800B clock controller. This is specifically
> > required for the SDHCI controller to function correctly under Linux.
> > 
> > The Linux 'sophgo,cv1800-clk' driver probes this device to determine
> > the clock tree configuration. This implementation sets the bypass
> > registers (CLK_BYP_0 and CLK_BYP_1) to 0xFFFFFFFF during reset,
> > matching the POR default state. This bypasses the PLLs and allows the
> > SDHCI and other peripherals to operate using the 25MHz reference clock.
> > 
> > Without this device, the SD card driver fails to initialize, preventing
> > the system from mounting the root filesystem from the SD card:
> > 
> > [    0.888739] Waiting for root device /dev/mmcblk0...
> > [   10.727739] mmc0: Timeout waiting for hardware cmd interrupt.
> > [   10.728042] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
> > [   10.728356] mmc0: sdhci: Sys addr:  0x00000002 | Version:  0x00002402
> > [   10.728618] mmc0: sdhci: Blk size:  0x00000000 | Blk cnt:  0x00000000
> > [   10.728919] mmc0: sdhci: Argument:  0x00000000 | Trn mode: 0x00000000
> > [   10.729271] mmc0: sdhci: Present:   0x01ff0000 | Host ctl: 0x00000001
> > [   10.729591] mmc0: sdhci: Power:     0x0000000f | Blk gap:  0x00000000
> > [   10.729903] mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000000
> > [   10.730223] mmc0: sdhci: Timeout:   0x00000000 | Int stat: 0x00000000
> > [   10.730537] mmc0: sdhci: Int enab:  0x00ff0083 | Sig enab: 0x00ff0083
> > [   10.730795] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
> > [   10.731005] mmc0: sdhci: Caps:      0x056900b9 | Caps_1:   0x00000000
> > [   10.731211] mmc0: sdhci: Cmd:       0x00000000 | Max curr: 0x00000000
> > [   10.731415] mmc0: sdhci: Resp[0]:   0x00000000 | Resp[1]:  0x00000000
> > [   10.731636] mmc0: sdhci: Resp[2]:   0x00000000 | Resp[3]:  0x00000000
> > [   10.731851] mmc0: sdhci: Host ctl2: 0x00000000
> > [   10.732018] mmc0: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x00000000
> > [   10.732229] mmc0: sdhci: ============================================
> > 
> > Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
> > ---
> >  hw/misc/Kconfig               |  3 ++
> >  hw/misc/cv1800b_clk.c         | 89 +++++++++++++++++++++++++++++++++++
> >  hw/misc/meson.build           |  1 +
> >  include/hw/misc/cv1800b_clk.h | 24 ++++++++++
> >  4 files changed, 117 insertions(+)
> >  create mode 100644 hw/misc/cv1800b_clk.c
> >  create mode 100644 include/hw/misc/cv1800b_clk.h
> > 
> > diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> > index 99bdf09219..42cdf771a4 100644
> > --- a/hw/misc/Kconfig
> > +++ b/hw/misc/Kconfig
> > @@ -254,4 +254,7 @@ config IOSB
> >  config XLNX_VERSAL_TRNG
> >      bool
> >  
> > +config SOPHGO_CV1800B_CLK
> > +    bool
> > +
> >  source macio/Kconfig
> > diff --git a/hw/misc/cv1800b_clk.c b/hw/misc/cv1800b_clk.c
> > new file mode 100644
> > index 0000000000..738f0910db
> > --- /dev/null
> > +++ b/hw/misc/cv1800b_clk.c
> > @@ -0,0 +1,89 @@
> > +/* SPDX-License-Identifier: GPL-2.0-or-later */
> > +/*
> > + * Sophgo CV1800B Clock Controller
> > + *
> > + * Copyright (c) 2026 Kuan-Wei Chiu <visitorckw@gmail.com>
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "hw/misc/cv1800b_clk.h"
> > +
> > +#define REG_CLK_BYP_0  (0x030 / 4)
> > +#define REG_CLK_BYP_1  (0x034 / 4)
> I suggest using the REG_BYTE_WIDTH macro instead of the constant value 4
> here and elsewhere.
> 
> #define REG_BYTE_WIDTH    (4)
> #define REG_CLK_BYP_0     (0x030 / REG_BYTE_WIDTH)
> #define REG_CLK_BYP_1     (0x034 / REG_BYTE_WIDTH)
> 
> You could also use `RegisterInfo` to define these register operations, so
> we don’t have to manually define these helper macros. Since this hardware
> is relatively simple, the current implementation is acceptable as well.
> 
Noted. Thanks.
I'll make this change when I respin this patchset.

Regards,
Kuan-Wei