From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v3 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs
Date: Wed, 13 May 2026 16:57:10 +0300 [thread overview]
Message-ID: <agSDNhRKBXcFV8a5@intel.com> (raw)
In-Reply-To: <e069a2d4892291c53d60415037a9d967fdae9f3a.1778666967.git.jani.nikula@intel.com>
On Wed, May 13, 2026 at 01:10:09PM +0300, Jani Nikula wrote:
> Call the platform specific display irq postinstall hooks via
> intel_display_irq_postinstall().
>
> Relocate the gen11 HAS_DISPLAY() check to
> intel_display_irq_postinstall(), as the funcs pointer won't be
> initialized for no display.
>
> v2:
> - relocate HAS_DISPLAY() (Sashiko)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 30 +++++++++++++------
> .../gpu/drm/i915/display/intel_display_irq.h | 7 +----
> drivers/gpu/drm/i915/i915_irq.c | 16 +++++-----
> drivers/gpu/drm/xe/display/xe_display.c | 2 +-
> 4 files changed, 31 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 62a849673454..1c3c8095765d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1981,7 +1981,7 @@ u32 i9xx_display_irq_enable_mask(struct intel_display *display)
> return enable_mask;
> }
>
> -void i915_display_irq_postinstall(struct intel_display *display)
> +static void i915_display_irq_postinstall(struct intel_display *display)
> {
> /*
> * Interrupt setup is already guaranteed to be single-threaded, this is
> @@ -1995,7 +1995,7 @@ void i915_display_irq_postinstall(struct intel_display *display)
> i915_enable_asle_pipestat(display);
> }
>
> -void i965_display_irq_postinstall(struct intel_display *display)
> +static void i965_display_irq_postinstall(struct intel_display *display)
> {
> /*
> * Interrupt setup is already guaranteed to be single-threaded, this is
> @@ -2057,7 +2057,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
> irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
> }
>
> -void vlv_display_irq_postinstall(struct intel_display *display)
> +static void vlv_display_irq_postinstall(struct intel_display *display)
> {
> spin_lock_irq(&display->irq.lock);
> if (display->irq.vlv_display_irqs_enabled)
> @@ -2262,7 +2262,7 @@ void valleyview_disable_display_irqs(struct intel_display *display)
> spin_unlock_irq(&display->irq.lock);
> }
>
> -void ilk_de_irq_postinstall(struct intel_display *display)
> +static void ilk_de_irq_postinstall(struct intel_display *display)
> {
> u32 display_mask, extra_mask;
>
> @@ -2306,7 +2306,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
> static void mtp_irq_postinstall(struct intel_display *display);
> static void icp_irq_postinstall(struct intel_display *display);
>
> -void gen8_de_irq_postinstall(struct intel_display *display)
> +static void gen8_de_irq_postinstall(struct intel_display *display)
> {
> u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
> GEN8_PIPE_CDCLK_CRC_DONE;
> @@ -2433,11 +2433,8 @@ static void icp_irq_postinstall(struct intel_display *display)
> irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
> }
>
> -void gen11_de_irq_postinstall(struct intel_display *display)
> +static void gen11_de_irq_postinstall(struct intel_display *display)
> {
> - if (!HAS_DISPLAY(display))
> - return;
> -
> gen8_de_irq_postinstall(display);
>
> intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> @@ -2445,30 +2442,37 @@ void gen11_de_irq_postinstall(struct intel_display *display)
>
> struct intel_display_irq_funcs {
> void (*reset)(struct intel_display *display);
> + void (*postinstall)(struct intel_display *display);
> };
>
> static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
> .reset = gen11_display_irq_reset,
> + .postinstall = gen11_de_irq_postinstall,
> };
>
> static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
> .reset = gen8_display_irq_reset,
> + .postinstall = gen8_de_irq_postinstall,
> };
>
> static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
> .reset = vlv_display_irq_reset,
> + .postinstall = vlv_display_irq_postinstall,
> };
>
> static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
> .reset = ilk_display_irq_reset,
> + .postinstall = ilk_de_irq_postinstall,
> };
>
> static const struct intel_display_irq_funcs i965_display_irq_funcs = {
> .reset = i9xx_display_irq_reset,
> + .postinstall = i965_display_irq_postinstall,
> };
>
> static const struct intel_display_irq_funcs i915_display_irq_funcs = {
> .reset = i9xx_display_irq_reset,
> + .postinstall = i915_display_irq_postinstall,
> };
>
> void intel_display_irq_reset(struct intel_display *display)
> @@ -2479,6 +2483,14 @@ void intel_display_irq_reset(struct intel_display *display)
> display->irq.funcs->reset(display);
> }
>
> +void intel_display_irq_postinstall(struct intel_display *display)
> +{
> + if (!HAS_DISPLAY(display))
> + return;
> +
> + display->irq.funcs->postinstall(display);
> +}
> +
> void intel_display_irq_init(struct intel_display *display)
> {
> spin_lock_init(&display->irq.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index 21b2145656cd..fd9873ce9755 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -59,14 +59,9 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
> void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>
> void intel_display_irq_reset(struct intel_display *display);
> +void intel_display_irq_postinstall(struct intel_display *display);
>
> u32 i9xx_display_irq_enable_mask(struct intel_display *display);
> -void i915_display_irq_postinstall(struct intel_display *display);
> -void i965_display_irq_postinstall(struct intel_display *display);
> -void vlv_display_irq_postinstall(struct intel_display *display);
> -void ilk_de_irq_postinstall(struct intel_display *display);
> -void gen8_de_irq_postinstall(struct intel_display *display);
> -void gen11_de_irq_postinstall(struct intel_display *display);
>
> u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
> void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c4f56a869910..c21b289b8007 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -724,7 +724,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen5_gt_irq_postinstall(to_gt(dev_priv));
>
> - ilk_de_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
> }
>
> static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -733,7 +733,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen5_gt_irq_postinstall(to_gt(dev_priv));
>
> - vlv_display_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
>
> intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
> @@ -744,7 +744,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> struct intel_display *display = dev_priv->display;
>
> gen8_gt_irq_postinstall(to_gt(dev_priv));
> - gen8_de_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
>
> gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
> }
> @@ -757,7 +757,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>
> gen11_gt_irq_postinstall(gt);
> - gen11_de_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
>
> gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
>
> @@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
>
> - gen11_de_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
>
> dg1_master_intr_enable(intel_uncore_regs(uncore));
> intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> @@ -790,7 +790,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen8_gt_irq_postinstall(to_gt(dev_priv));
>
> - vlv_display_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
>
> intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
> @@ -888,7 +888,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
>
> - i915_display_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
> }
>
> static irqreturn_t i915_irq_handler(int irq, void *arg)
> @@ -997,7 +997,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
>
> gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
>
> - i965_display_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
> }
>
> static irqreturn_t i965_irq_handler(int irq, void *arg)
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index ba3225878c61..62e5d38938eb 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -246,7 +246,7 @@ void xe_display_irq_postinstall(struct xe_device *xe)
> if (!xe->info.probe_display)
> return;
>
> - gen11_de_irq_postinstall(display);
> + intel_display_irq_postinstall(display);
> }
>
> static bool suspend_to_idle(void)
> --
> 2.47.3
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2026-05-13 13:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 10:10 [PATCH v3 0/6] drm/i915: add display irq hooks Jani Nikula
2026-05-13 10:10 ` [PATCH v3 1/6] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall() Jani Nikula
2026-05-13 13:53 ` Ville Syrjälä
2026-05-13 10:10 ` [PATCH v3 2/6] drm/i915/irq: constify pipe stats parameters Jani Nikula
2026-05-13 13:54 ` Ville Syrjälä
2026-05-13 10:10 ` [PATCH v3 3/6] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset() Jani Nikula
2026-05-13 13:56 ` Ville Syrjälä
2026-05-13 10:10 ` [PATCH v3 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs Jani Nikula
2026-05-13 13:57 ` Ville Syrjälä [this message]
2026-05-13 10:10 ` [PATCH v3 5/6] drm/i915/irq: add intel_display_irq_ack() " Jani Nikula
2026-05-13 14:30 ` Ville Syrjälä
2026-05-13 16:15 ` Jani Nikula
2026-05-13 10:10 ` [PATCH v3 6/6] drm/i915/irq: add intel_display_irq_handler() " Jani Nikula
2026-05-13 12:38 ` Ville Syrjälä
2026-05-13 12:22 ` ✗ i915.CI.BAT: failure for drm/i915: add display irq hooks (rev2) Patchwork
2026-05-13 12:22 ` Patchwork
2026-05-13 12:22 ` Patchwork
2026-05-13 12:22 ` Patchwork
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