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Thu, 14 May 2026 11:07:23 -0700 (PDT) Received: from google.com ([118.150.148.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19c7c74fsm4330143b3a.49.2026.05.14.11.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2026 11:07:22 -0700 (PDT) Date: Fri, 15 May 2026 02:07:18 +0800 From: Kuan-Wei Chiu To: Chao Liu Cc: pbonzini@redhat.com, marcandre.lureau@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, christoph.muellner@vrull.eu, farosas@suse.de, lvivier@redhat.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, jserv@ccns.ncku.edu.tw, eleanor15x@gmail.com, marscheng@google.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v2 1/6] target/riscv: Add stubs for T-Head PMU CSRs Message-ID: References: <20260514011528.1263665-1-visitorckw@gmail.com> <20260514011528.1263665-2-visitorckw@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=visitorckw@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Chao, On Thu, May 14, 2026 at 10:48:07AM +0800, Chao Liu wrote: > On Thu, May 14, 2026 at 01:15:23AM +0000, Kuan-Wei Chiu wrote: > > T-Head CPUs use custom CSRs for performance monitoring, specifically > > mcounterinten (0x7ca) and mcounterof (0x7cb). [1] > > > > Since we don't implement these custom PMU registers yet, the system > > crashes with an illegal instruction trap when OpenSBI like this: > > > > system_opcode_insn: Failed to access CSR 0x7ca from M-mode > > sbi_trap_error: hart0: trap1: illegal instruction handler failed (error -1) > > > > Add simple read/write stubs for these two CSRs. By silently ignoring > > writes and returning 0 on reads, we prevent the fatal exceptions and > > allow to continue normally. > > > > Link: https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource/XuanTie-OpenC906-UserManual.pdf [1] > > Signed-off-by: Kuan-Wei Chiu > > --- > > target/riscv/th_csr.c | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c > > index 49eb7bbab5..b095364c31 100644 > > --- a/target/riscv/th_csr.c > > +++ b/target/riscv/th_csr.c > > @@ -21,12 +21,19 @@ > > #include "cpu_vendorid.h" > > > > #define CSR_TH_SXSTATUS 0x5c0 > > +#define CSR_TH_MCOUNTERINTEN 0x7ca > > +#define CSR_TH_MCOUNTEROF 0x7cb > > > > /* TH_SXSTATUS bits */ > > #define TH_SXSTATUS_UCME BIT(16) > > #define TH_SXSTATUS_MAEE BIT(21) > > #define TH_SXSTATUS_THEADISAEE BIT(22) > > > > +static RISCVException mmode(CPURISCVState *env, int csrno) > > +{ > > + return RISCV_EXCP_NONE; > > +} > We can add an RVM extension check, similar in form to smode(): > > static RISCVException mmode(CPURISCVState *env, int csrno) > { > if (riscv_has_ext(env, RVM)) { Thanks for your review. However, I think this might not be correct. IIUC, RVM represents the standard M extension for integer multiplication and division instructions, rather than indicating whether M mode is implemented. Is it even possible for a riscv machine implementation to not have M mode? Looking at the misa csr description in the spec, the 'S' and 'U' bits specifically denote the implementation of supervisor and user modes, respectively, but there is no corresponding bit for M mode. I assume this implies M mode is unconditionally required? > return RISCV_EXCP_NONE; > } > > return RISCV_EXCP_ILLEGAL_INST; > } > > For your reference, I have added more T-Head CSR support in the > K230 patchset. > > https://lore.kernel.org/qemu-devel/1c7319cd00a50bffeb41f9cc13339a8cd0c07350.1778516731.git.chao.liu.zevorn@gmail.com/ It looks like your patch covers much more ground than mine and has already received quite a few reviews. I assume once your series is merged, I can simply drop my patch #1. So I guess the most sensible workflow here is for me to wait until your patchset is merged into the subsystem maintainer's tree (assuming it will route through Alistair's tree [1] I guess?, please correct me if I'm wrong!), and then I'll rebase my series on top of it and send out v3? [1]: https://github.com/alistair23/qemu.git riscv-to-apply.next Regards, Kuan-Wei > > As for this patch, I think the other changes look mostly fine. > > Thanks, > Chao > > + > > static RISCVException smode(CPURISCVState *env, int csrno) > > { > > if (riscv_has_ext(env, RVS)) { > > @@ -49,11 +56,34 @@ static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, > > return RISCV_EXCP_NONE; > > } > > > > +static RISCVException read_th_pmu(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val = 0; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_th_pmu(CPURISCVState *env, int csrno, > > + target_ulong val, uintptr_t retaddr) > > +{ > > + return RISCV_EXCP_NONE; > > +} > > + > > const RISCVCSR th_csr_list[] = { > > { > > .csrno = CSR_TH_SXSTATUS, > > .insertion_test = test_thead_mvendorid, > > .csr_ops = { "th.sxstatus", smode, read_th_sxstatus } > > }, > > + { > > + .csrno = CSR_TH_MCOUNTERINTEN, > > + .insertion_test = test_thead_mvendorid, > > + .csr_ops = { "th.mcounterinten", mmode, read_th_pmu, write_th_pmu } > > + }, > > + { > > + .csrno = CSR_TH_MCOUNTEROF, > > + .insertion_test = test_thead_mvendorid, > > + .csr_ops = { "th.mcounterof", mmode, read_th_pmu, write_th_pmu } > > + }, > > { } > > }; > > -- > > 2.54.0.563.g4f69b47b94-goog > >