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Thu, 14 May 2026 20:14:15 -0700 (PDT) Received: from ZEVORN-PC.localdomain ([64.186.250.142]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302977a9474sm5473564eec.25.2026.05.14.20.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2026 20:14:14 -0700 (PDT) Date: Fri, 15 May 2026 11:14:07 +0800 From: Chao Liu To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, leif.lindholm@oss.qualcomm.com, andrew.jones@oss.qualcomm.com, Fei Wu Subject: Re: [PATCH v6 2/4] target/riscv: Add server platform reference cpu Message-ID: References: <20260514204640.2540054-1-daniel.barboza@oss.qualcomm.com> <20260514204640.2540054-3-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260514204640.2540054-3-daniel.barboza@oss.qualcomm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1344; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, May 14, 2026 at 05:46:38PM -0300, Daniel Henrique Barboza wrote: > From: Fei Wu > > The harts requirements of RISC-V server platform [1] require RVA23 ISA > profile support and others. > > This patch provides a new "riscv-server-ref" CPU to go along with the > future "riscv-server-ref" board. > > [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc > > Signed-off-by: Fei Wu > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Thanks, Chao > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 11 +++++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 30dcdcfaae..a150acd151 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -42,6 +42,7 @@ > #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") > #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") > #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") > +#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-ref") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") > #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 586683b28a..c81aab08cd 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3401,6 +3401,17 @@ static const TypeInfo riscv_cpu_type_infos[] = { > #endif > ), > > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU, > + .misa_mxl_max = MXL_RV64, > + .profile = &RVA23S64, > + > + .cfg.ext_zkr = true, > + .cfg.ext_svadu = true, > + .cfg.ext_sdext = true, > + > + .cfg.max_satp_mode = VM_1_10_SV48, > + ), > + > #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, > .cfg.max_satp_mode = VM_1_10_SV57, > -- > 2.43.0 >