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Mon, 18 May 2026 14:56:58 -0700 (PDT) Received: from localhost ([64.186.250.142]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302978afdd3sm14960297eec.29.2026.05.18.14.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 14:56:58 -0700 (PDT) Date: Tue, 19 May 2026 05:56:55 +0800 From: Chao Liu To: Jim Shu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: Re: [PATCH 1/4] hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode Message-ID: References: <20260428160103.3551125-1-jim.shu@sifive.com> <20260428160103.3551125-2-jim.shu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260428160103.3551125-2-jim.shu@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1343; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Apr 29, 2026 at 12:01:00AM +0800, Jim Shu wrote: > According to the AIA spec ch4.7 ("Precise effects on interrupt-pending > bits"), pending bit of APLIC should be set/cleared whenever the > rectified input value is high/low in the both level-trigger mode > and direct delivery mode. > > Currently, QEMU APLIC only clears the pending bit when interrupt is > claimed in APLIC, but not clears it when the rectified input value is > low. (e.g. IRQ source signal is low in the LEVEL_HIGH/Level1 mode). > The software may receive an additional IRQ if the peripheral > triggers one after the software clears the APLIC IRQ but before it > clears the peripheral's IRQ. > > Thus, we also clear the pending bit via the rectified input value in the > level-trigger mode. > > This change doesn't affect MSI delivery mode. Calling > riscv_aplic_msi_irq_update() when IRQ pending is low will do nothing. > > Signed-off-by: Jim Shu Reviewed-by: Chao Liu Thanks, Chao > --- > hw/intc/riscv_aplic.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c > index 8f700431114..791e0b01b96 100644 > --- a/hw/intc/riscv_aplic.c > +++ b/hw/intc/riscv_aplic.c > @@ -591,14 +591,14 @@ static void riscv_aplic_request(void *opaque, int irq, int level) > } > break; > case APLIC_SOURCECFG_SM_LEVEL_HIGH: > - if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) { > - riscv_aplic_set_pending_raw(aplic, irq, true); > + if ((level > 0) != !!(state & APLIC_ISTATE_PENDING)) { > + riscv_aplic_set_pending_raw(aplic, irq, level > 0); > update = true; > } > break; > case APLIC_SOURCECFG_SM_LEVEL_LOW: > - if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) { > - riscv_aplic_set_pending_raw(aplic, irq, true); > + if ((level <= 0) != !!(state & APLIC_ISTATE_PENDING)) { > + riscv_aplic_set_pending_raw(aplic, irq, level <= 0); > update = true; > } > break; > -- > 2.43.0 >