Re: [PATCH v4 2/2] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller

["Roger Pau Monné" <roger.pau@citrix.com>]

On Tue, Jun 02, 2026 at 01:34:21PM +0800, Jiaqing Zhao wrote:
> Add a PCI device table entry and matching parameter for the ASIX
> AX99100 PCIe to Multi-I/O controller [125b:9910]. Each port on the
> chip is a standalone PCI function, with UART registers on its I/O
> BAR0.
> 
> Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
>  xen/drivers/char/ns16550.c | 15 +++++++++++++++
>  xen/include/xen/pci_ids.h  |  2 ++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> index cf10a06a3d..26503070dc 100644
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -96,6 +96,7 @@ struct ns16550_config {
>          param_exar_xr17v358,
>          param_intel_lpss,
>          param_wch_ch382,
> +        param_asix,
>      } param;
>  };
>  
> @@ -872,6 +873,14 @@ static const struct ns16550_config_param __initconst uart_param[] = {
>          .bar0 = 1,
>          .max_ports = 2,
>      },
> +    [param_asix] = {
> +        .base_baud = 115200,
> +        .reg_width = 1,
> +        .fifo_size = 256,
> +        .lsr_mask = UART_LSR_THRE,
> +        .bar0 = 1,

Same comment about using 1 instead of true, the rest seem reasonable:

Acked-by: Roger Pau Monné <roger.pau@citrix.com>

Thanks, Roger.