Re: [PATCH v6 0/7] riscv: add initial sdext support

[Chao Liu <chao.liu.zevorn@gmail.com>]

On Wed, May 27, 2026 at 10:13:04AM +0800, Daniel Henrique Barboza wrote:
> Hi Chao!
> 
> 
> Can you please re-send this series?  We did changes in the last PR that
> will conflict with what you did - most likely a trivial conflict in
> patch 2.
> 
> I'll resend patch 1 myself.  Feel free to pick the rebased version to
> include in your v7.

Sure, I’ll resend the v7 patches after you resend patch 1.

Thanks,
Chao
> 
> 
> Cheers,
> Daniel
> 
> 
> 
> 
> > Hi,
> > 
> > This v6 series is rebased on Alistair's riscv-to-apply.next branch [1].
> > 
> > The implementation follows RISC-V Debug Specification 1.0 [2].
> > 
> > It introduces the sdext/sdtrig config bits, DCSR/DPC/DSCRATCH state,
> > Debug Mode enter/leave helpers, DRET, EBREAK entry, single-step, and
> > trigger action=debug mode.
> > 
> > To reduce review load, this series focuses on the Sdext features first.
> > The Debug Module (DM) and related flows will follow in a later series.
> > 
> > Changes in v6:
> > - Rebased onto latest riscv-to-apply.next
> > 
> > Changes in v5:
> > - Patch 2: removed redundant `cpu->cfg.ext_sdext = false;` in
> >    riscv_cpu_init() since it's already set to false in MULTI_EXT_CFG_BOOL.
> >    (Daniel)
> > - Patch 7: changed LOG_UNIMP to LOG_GUEST_ERROR for invalid trigger
> >    action=debug mode when Sdext is not enabled. LOG_UNIMP is reserved
> >    for unimplemented features, while LOG_GUEST_ERROR is for invalid
> >    guest actions. (Daniel)
> > 
> > Changes in v4:
> > - Fixed linux-user build errors: moved debug_mode/dcsr/dpc/dscratch
> >    fields inside #ifndef CONFIG_USER_ONLY block in cpu.h, and wrapped
> >    all code using these fields with proper guards. (Daniel)
> > - Updated dependency from single patch (patch 5 only) to patches 1-5
> >    of Max Chou's "Add Zvfbfa extension support" v2 series to avoid
> >    compilation errors.
> > 
> > Changes in v3:
> > - Rebase onto Alistair's riscv-to-apply.next branch.
> > - Depend on Max Chou's patch "target/riscv: Use the tb->cs_bqse as
> >    the extend tb flags." (not included; apply it first) [3].
> > - Patch 2: default sdext to false in riscv_cpu_extensions.
> > 
> > Changes in v2:
> > - Drop the RHCT expected AML update from this series.
> > - Replace the split sdext/sdtrig config bits patch with deprecating the
> >    'debug' CPU property.
> > - Rebase and update patch subjects to target/riscv prefix.
> > 
> > Changes in v1:
> > - Debug Mode entry/exit updates DCSR/DPC and restores execution via DRET.
> > - EBREAK honors DCSR ebreak bits and enters Debug Mode when enabled.
> > - Single-step uses DCSR.STEP with a TB flag and a helper at TB exit.
> >    It references Max Chou's patch "target/riscv: Use the tb->cs_bqse as
> >    the extend tb flags." [3].
> > - Sdtrig supports action=debug mode for mcontrol/mcontrol6 and reports
> >    inst-count triggers in tinfo.
> > 
> > ---
> > 
> > Differences vs Debug Spec (known gaps):
> > - No Debug Module (no DMI, dmcontrol/dmstatus, haltreq/resumereq).
> > - No debug ROM, program buffer, abstract commands, or SBA.
> > - Resume is modeled by leaving Debug Mode at cpu_exec_enter.
> > - Step/exception ordering is simplified: if the stepped instruction
> >    traps, the normal exception is taken and Debug Mode is not forced.
> > - Several DCSR fields are not fully modeled (stopcount/stoptime, etc).
> > 
> > Roadmap (next stage, DM focus):
> > 1) Add a DM core with DMI access and hart state tracking.
> > 2) Implement halt/resume handshake and move Debug Mode transitions
> >     under DM control.
> > 3) Add debug ROM, program buffer, and abstract commands for GPR/CSR
> >     and memory access.
> > 4) Add SBA if required by tooling.
> > 5) Tighten ordering rules for step/exception/trigger priorities.
> > 
> > CI (all jobs passed except check-patch which flags pre-existing
> > upstream style issues, not related to this series) [4].
> > 
> > References:
> > [1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next
> > [2] https://github.com/riscv/riscv-debug-spec/releases/tag/1.0
> > [3] https://lore.kernel.org/qemu-devel/20260108132631.9429-1-max.chou@sifive.com/
> > [4] https://gitlab.com/TaoTang/qemu/-/pipelines/2446308835
> > 
> > 
> > Thanks,
> > Chao
> > 
> > Chao Liu (6):
> >    target/riscv: add sdext debug CSRs state
> >    target/riscv: add sdext Debug Mode helpers
> >    target/riscv: add dret instruction
> >    target/riscv: add sdext enter Debug Mode on ebreak
> >    target/riscv: add sdext single-step support
> >    target/riscv: add sdtrig trigger action=debug mode
> > 
> > Daniel Henrique Barboza (1):
> >    target/riscv: deprecate 'debug' CPU property
> > 
> >   docs/about/deprecated.rst                     |   7 +
> >   include/exec/translation-block.h              |   4 +-
> >   target/riscv/cpu.c                            |  59 +++++++-
> >   target/riscv/cpu.h                            |   9 ++
> >   target/riscv/cpu_bits.h                       |  33 +++++
> >   target/riscv/cpu_cfg_fields.h.inc             |   3 +-
> >   target/riscv/cpu_helper.c                     |  90 ++++++++++++
> >   target/riscv/csr.c                            | 128 +++++++++++++++++-
> >   target/riscv/debug.c                          |  58 +++++++-
> >   target/riscv/helper.h                         |   3 +
> >   target/riscv/insn32.decode                    |   1 +
> >   .../riscv/insn_trans/trans_privileged.c.inc   |  24 ++++
> >   target/riscv/machine.c                        |  44 ++++--
> >   target/riscv/op_helper.c                      |  70 ++++++++++
> >   target/riscv/tcg/tcg-cpu.c                    |  21 ++-
> >   target/riscv/translate.c                      |  15 +-
> >   16 files changed, 544 insertions(+), 25 deletions(-)
> > 
>