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Thu, 28 May 2026 06:39:07 -0700 (PDT) Received: from x1.local ([142.189.10.167]) by smtp.gmail.com with ESMTPSA id af79cd13be357-914f86e9bf5sm814983685a.8.2026.05.28.06.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 06:39:07 -0700 (PDT) Date: Thu, 28 May 2026 09:39:06 -0400 From: Peter Xu To: BALATON Zoltan Cc: Peter Maydell , qemu-devel@nongnu.org, Akihiko Odaki , Paolo Bonzini , Max Filippov , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH v5 1/7] memory: Export memory_region_set_ops() Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, May 25, 2026 at 10:57:39PM +0200, BALATON Zoltan wrote: > On Mon, 25 May 2026, Peter Maydell wrote: > > On Mon, 25 May 2026 at 16:47, BALATON Zoltan wrote: > > > > > > Make memory_region_set_ops() function public. In some cases such as > > > when devices have configurable endianness or different behaviour based > > > on settings it is necessary to change the ops callback after the > > > memory region is created. Export memory_region_set_ops() function for > > > this. > > > > If some other CPU is in the middle of using the old MemoryRegionOps > > when the device swaps them out under its feet, what happens? > > In my limited test with PPC and ati-vga this seems to work and the switch > would happen in device register write so nothing else is expected to run > accessing the device at the same time at that point. I can't tell for all > possible cases but that would then be a problem in the caller not in this > function. Callers are expected to call it when appropriate which I could > mention in the doc comment if needed. > > > You could also remove the old MR from its container and add a different > > one with the different behaviour when the guest changes the config, > > or have both of them in the container and toggle which is visible > > with memory_region_set_enabled(). That might potentially be more > > awkward but it would avoid having to look into the memory region > > API internals. > > That could also work if I had a container but it's switching the endianness > of a PCI BAR which is registered with pci_register_bar() so it's easiest to > switch the ops on the region than hacking around it using two more otherwise > unneeded memory regions as I also can't swap PCI BARs so it would need a > container aditionally to two regions using the same callbacks just with > different endianness. Allowing setting the ops of a single region seems > simpler. I think PeterM's proposal makes more sense. Having two MRs registered under the same offset of parent and dynamically enable/disable seems to be a common way to solve similar problems in QEMU. I don't see why it is hacky if we can allow dynamic flip of mr->ops, which smells more risky. Exporting that API may invite more abuse, which I'm not sure it's good. The other thing I want to mention is having ops flippable relies on "BQL serializes everything", but it's already not true with exceptions like HPET, see memory_region_enable_lockless_io(). I think this will introduce tech debts that we don't necessarily need. Thanks, -- Peter Xu