From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com,
jani.nikula@intel.com
Subject: Re: [PATCH v7 09/15] drm/i915/cmtg: Modify existing hook to disable CMTG
Date: Fri, 29 May 2026 14:02:06 +0300 [thread overview]
Message-ID: <ahlyLvT7ZqvzaxwQ@intel.com> (raw)
In-Reply-To: <20260526133811.2621675-10-animesh.manna@intel.com>
On Tue, May 26, 2026 at 07:08:05PM +0530, Animesh Manna wrote:
> From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
>
> Earlier cmtg_disable() used to disable all instances of CMTG
> which cannot handle individual request for specific CMTG instance.
> Introduce cmtg_disable_all() which will disable all cmtg instances
> and cmtg_disable() only disable specific instance.
>
> v2:
> - Use intel_de_rmw to simplify. [Uma]
>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 60 ++++++++++++++-----
> drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 1 +
> 3 files changed, 47 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 34715280d65d..643e2e846d25 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -82,6 +82,18 @@ static void intel_cmtg_dump_config(struct intel_display *display,
> str_yes_no(cmtg_config->trans_b_secondary));
> }
>
> +static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
> +{
> + switch (cpu_transcoder) {
> + case TRANSCODER_A:
> + return TRANSCODER_CMTG0;
> + case TRANSCODER_B:
> + return TRANSCODER_CMTG1;
> + default:
> + return INVALID_TRANSCODER;
> + }
> +}
> +
> static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
> enum transcoder trans)
> {
> @@ -125,8 +137,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
> return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
> }
>
> -static void intel_cmtg_disable(struct intel_display *display,
> - struct intel_cmtg_config *cmtg_config)
> +static void intel_cmtg_disable_all(struct intel_display *display,
> + struct intel_cmtg_config *cmtg_config)
> {
> u32 clk_sel_clr = 0;
> u32 clk_sel_set = 0;
> @@ -157,6 +169,36 @@ static void intel_cmtg_disable(struct intel_display *display,
> intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
>
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
> + u32 clk_sel_clr = 0;
> +
> + if (!intel_cmtg_is_allowed(crtc_state))
> + return;
I think we just want to track the cmtg transcoder in the crtc state,
instead of this stuff that just assumes things.
> +
> + intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
> + VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
> +
> + intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
> + CMTG_SECONDARY_MODE, 0);
> +
> + intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
> +
> + if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
> + drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
> + transcoder_name(cpu_transcoder));
> + return;
> + }
> +
> + clk_sel_clr = cpu_transcoder == TRANSCODER_A ? CMTG_CLK_SEL_A_MASK : CMTG_CLK_SEL_B_MASK;
> + intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, 0);
> +
> + drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
> +}
> +
> /*
> * Read out CMTG configuration and, on platforms that allow disabling it without
> * a modeset, do it.
> @@ -184,7 +226,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
> if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
> return;
>
> - intel_cmtg_disable(display, &cmtg_config);
> + intel_cmtg_disable_all(display, &cmtg_config);
> }
>
> bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> @@ -221,18 +263,6 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
> intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
>
> -static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
> -{
> - switch (cpu_transcoder) {
> - case TRANSCODER_A:
> - return TRANSCODER_CMTG0;
> - case TRANSCODER_B:
> - return TRANSCODER_CMTG1;
> - default:
> - return INVALID_TRANSCODER;
> - }
> -}
> -
> void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 12abbafa7d08..79785afccc51 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
> struct intel_display;
> struct intel_crtc_state;
>
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index a93236bf7b75..240a02cd4a3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -22,5 +22,6 @@
> _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
> #define CMTG_ENABLE REG_BIT(31)
> #define CMTG_SYNC_TO_PORT REG_BIT(29)
> +#define CMTG_STATE REG_BIT(23)
>
> #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2026-05-29 11:02 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 13:37 [PATCH v7 00/15] CMTG enablement Animesh Manna
2026-05-26 13:37 ` [PATCH v7 01/15] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-05-29 10:22 ` Dibin Moolakadan Subrahmanian
2026-05-26 13:37 ` [PATCH v7 02/15] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-05-26 13:37 ` [PATCH v7 03/15] drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info Animesh Manna
2026-05-26 13:38 ` [PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-05-29 10:58 ` Ville Syrjälä
2026-06-01 14:31 ` Manna, Animesh
2026-06-02 8:31 ` Shankar, Uma
2026-05-26 13:38 ` [PATCH v7 05/15] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-05-26 13:38 ` [PATCH v7 06/15] drm/i915/cmtg: Set transcoder mn for CMTG Animesh Manna
2026-05-26 13:38 ` [PATCH v7 07/15] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-05-26 13:38 ` [PATCH v7 08/15] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-05-29 10:27 ` Dibin Moolakadan Subrahmanian
2026-05-29 10:52 ` Ville Syrjälä
2026-06-01 13:39 ` Manna, Animesh
2026-05-26 13:38 ` [PATCH v7 09/15] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-05-29 11:02 ` Ville Syrjälä [this message]
2026-06-01 14:43 ` Manna, Animesh
2026-05-26 13:38 ` [PATCH v7 10/15] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-05-29 14:15 ` Dibin Moolakadan Subrahmanian
2026-06-03 12:22 ` Manna, Animesh
2026-05-26 13:38 ` [PATCH v7 11/15] drm/i915/cmtg: Add CMTG HWGB programming Animesh Manna
2026-05-26 13:38 ` [PATCH v7 12/15] drm/i915/cmtg: Add CMTG scan line programming Animesh Manna
2026-05-26 13:38 ` [PATCH v7 13/15] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-05-29 14:28 ` Dibin Moolakadan Subrahmanian
2026-06-03 12:27 ` Manna, Animesh
2026-05-26 13:38 ` [PATCH v7 14/15] drm/i915/cmtg: Restore CMTG after DC6 exit Animesh Manna
2026-05-26 13:38 ` [PATCH v7 15/15] [Not for Review] Debug patch Animesh Manna
2026-05-26 15:02 ` ✓ CI.KUnit: success for CMTG enablement (rev8) Patchwork
2026-05-26 16:10 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-26 18:01 ` ✓ i915.CI.BAT: success for CMTG enablement (rev7) Patchwork
2026-05-26 18:30 ` ✓ Xe.CI.FULL: success for CMTG enablement (rev8) Patchwork
2026-05-27 1:52 ` ✗ i915.CI.Full: failure for CMTG enablement (rev7) Patchwork
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