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Fri, 29 May 2026 09:44:51 -0700 (PDT) Received: from linaro.org ([2a10:d582:31e:0:9be1:73c8:1a1e:445a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45ef34a03f8sm5008748f8f.7.2026.05.29.09.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 09:44:51 -0700 (PDT) Date: Fri, 29 May 2026 17:44:49 +0100 From: Jim MacArthur To: Richard Henderson Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH 3/5] target/arm/ptw.c: Add Granule Bypass Windows Message-ID: References: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> <20260528-jmac-gpc3b-v1-3-d34c46c5069f@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=jim.macarthur@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Thu, May 28, 2026 at 11:52:09AM -0700, Richard Henderson wrote: > On 5/28/26 08:34, Jim MacArthur wrote: > > + /* > > + * GPC Priority 1 (R_GMGRR): > > + * If GPCCR_EL3.GPCBW is 1 and the configuration GPCBW > > + * is invalid, the access fails as GPT walk fault at level 0. > > + */ > > + if (FIELD_EX64(gpccr, GPCCR, GPCBW)) { > > + /* > > + * GPCBW is invalid if the base address is: > > + * not aligned to the size programmed in BWSIZE, or > > + * greater than or equal to the stride value configured by BWSTRIDE. > > + */ > > + uint64_t bw_size_mask = -1L << (bw_size_field + 31); > > + if (bw_start & bw_size_mask) { > > + goto fault_walk; > > + } > > + if (bw_start & bw_stride_mask) { > > + goto fault_walk; > > + } > > + } > > + > > switch (FIELD_EX64(gpccr, GPCCR, PGS)) { > > ... here. > > None of the checks you're adding are correct: > - Missing size and stride validation, > - Alignment check vs size is incorrect; you wanted > > bw_start & MAKE_64BIT_MASK(0, bw_size + BW_ADDR_SHIFT) > > - Check vs stride is incorrect; you wanted bw_stride <= bw_addr. > > See GPCRegistersConsistent(). Thanks for the review Richard; the bw_size_mask check was indeed wrong. On bw_stride_mask: it was intended to keep the high bits in bw_stride_mask hence this bitwise comparison should have been equivalent to bw_stride <= bw_addr; in fact the other use of bw_stride_mask was incorrect. However, since both Arm and Intel GCC produce roughly the same code for both I will replace it with the more readable arithmetic operation. On size and stride validation: there are reserved values for these fields, but the ARM does not say explicitly (that I can see) that they make GPCBW /invalid/, so it wasn't clear to me that we should fault on these. Jim