Re: [PATCH] PCI/P2PDMA: Add Intel QAT, DSA, IAA devices to whitelist

[Lukas Wunner <lukas@wunner.de>]

On Thu, Jun 04, 2026 at 09:21:50AM -0600, Logan Gunthorpe wrote:
> On 2026-06-04 5:50 a.m., Lukas Wunner wrote:
> > The first device on a PCI root bus determines whether the host bridge is
> > whitelisted for P2PDMA.  All Intel Xeon chips since Ice Lake (ICX, 2021)
> > expose a device with ID 0x09a2 as first device.  It is loosely associated
> > with the IOMMU.  All these Xeon chips support P2PDMA, so since the
> > addition of the device with commit feaea1fe8b36 ("PCI/P2PDMA: Add Intel
> > 3rd Gen Intel Xeon Scalable Processors to whitelist"), P2PDMA has been
> > allowed on all new Xeons without the need to amend the whitelist:
[...]
> > However these Xeons also expose accelerators as first device on a root bus
> > of its own:
> > 
> >   QuickAssist Technology (QAT, crypto & compression accelerator)
> >   Data Streaming Accelerator (DSA, dma engine)
> >   In-Memory Analytics Accelerator (IAA, dma engine)
> > 
> > Whitelist them for P2PDMA as well.  Move their Device ID macros from the
> > accelerator drivers to <linux/pci_ids.h> for reuse by P2PDMA code.
> 
> I'm sorry, I don't fully understand this. Are QAT devices functioning as
> root ports? Are there devices in the tree that are doing P2P
> transactions through theme? That surprises me.

These accelerators are RCiEPs, each located on a Host Bridge by itself.
The idea is that users should be able to set up P2PDMA between these
accelerators and other devices.

Thanks,

Lukas