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Sat, 06 Jun 2026 01:52:12 -0700 (PDT) Received: from v4bel ([58.123.110.97]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c16649d2dfsm116177535ad.75.2026.06.06.01.52.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jun 2026 01:52:12 -0700 (PDT) Date: Sat, 6 Jun 2026 17:52:08 +0900 From: Hyunwoo Kim To: Marc Zyngier Cc: tabba@google.com, oupton@kernel.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, imv4bel@gmail.com Subject: Re: [PATCH v2 2/2] KVM: arm64: Bound used_lrs when flushing the pKVM hyp vCPU Message-ID: References: <20260604151210.1304051-1-imv4bel@gmail.com> <20260604151210.1304051-3-imv4bel@gmail.com> <86zf19tlcu.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86zf19tlcu.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260606_015214_091879_C85AB9EC X-CRM114-Status: GOOD ( 31.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 05, 2026 at 09:58:09AM +0100, Marc Zyngier wrote: > On Thu, 04 Jun 2026 16:12:03 +0100, > Hyunwoo Kim wrote: > > > > flush_hyp_vcpu() copies the host vGIC state into the hyp's private vCPU > > on every run. The vGIC list register save and restore use used_lrs as > > their loop bound and expect it to stay within the number of implemented > > list registers. While this is generally the case, flush_hyp_vcpu() > > copies vgic_v3 verbatim and does not enforce this, so a value provided > > by the host is used at EL2 to index vgic_lr[] and access ICH_LR_EL2 > > (host -> EL2). > > > > Fix by clamping used_lrs to the number of implemented list registers > > after the copy, as the trusted path already does in > > vgic_flush_lr_state(). > > > > Fixes: be66e67f1750 ("KVM: arm64: Use the pKVM hyp vCPU structure in handle___kvm_vcpu_run()") > > Signed-off-by: Hyunwoo Kim > > --- > > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > > index 02c5d6e5abcbf..cd807fdb11ba8 100644 > > --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c > > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > > @@ -7,6 +7,7 @@ > > #include > > #include > > > > +#include > > #include > > #include > > #include > > @@ -142,6 +143,13 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) > > > > hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3 = host_vcpu->arch.vgic_cpu.vgic_v3; > > > > + /* Bound used_lrs by the number of implemented list registers. */ > > + if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) > > There is no pKVM support without a GICv3 CPU interface, and absolutely > everything already assumes it. Why do we need this extra check? > > > + hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3.used_lrs = > > + min_t(unsigned int, > > + hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3.used_lrs, > > + (read_gicreg(ICH_VTR_EL2) & 0xf) + 1); > > + > > Reading ICH_VTR_EL2 on each entry is going to cause some really heavy > trapping under NV, and we should avoid this. > > kvm_vgic_global_state.nr_lr contains this information, and it should > only be a matter of replicating it (or compute it once) at init time. Does this approach look reasonable to you? --- diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index 8d06b62e7188..25199769a1d6 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -157,5 +157,6 @@ extern unsigned long kvm_nvhe_sym(__icache_flags); extern unsigned int kvm_nvhe_sym(kvm_arm_vmid_bits); extern unsigned int kvm_nvhe_sym(kvm_host_sve_max_vl); extern unsigned long kvm_nvhe_sym(hyp_nr_cpus); +extern unsigned int kvm_nvhe_sym(hyp_vgic_nr_lr); #endif /* __ARM64_KVM_HYP_H__ */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 9453321ef8c6..891fe2c7b854 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2426,6 +2426,7 @@ static int __init init_subsystems(void) switch (err) { case 0: vgic_present = true; + kvm_nvhe_sym(hyp_vgic_nr_lr) = kvm_vgic_global_state.nr_lr; break; case -ENODEV: case -ENXIO: diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 06db299c37a8..8bb9362bc284 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -128,6 +128,9 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) hyp_vcpu->vcpu.arch.ctxt = host_vcpu->arch.ctxt; + /* A guest context must keep a NULL __hyp_running_vcpu. */ + hyp_vcpu->vcpu.arch.ctxt.__hyp_running_vcpu = NULL; + hyp_vcpu->vcpu.arch.mdcr_el2 = host_vcpu->arch.mdcr_el2; hyp_vcpu->vcpu.arch.hcr_el2 &= ~(HCR_TWI | HCR_TWE); hyp_vcpu->vcpu.arch.hcr_el2 |= READ_ONCE(host_vcpu->arch.hcr_el2) & @@ -139,6 +142,12 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3 = host_vcpu->arch.vgic_cpu.vgic_v3; + /* Bound used_lrs by the number of implemented list registers. */ + hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3.used_lrs = + min_t(unsigned int, + hyp_vcpu->vcpu.arch.vgic_cpu.vgic_v3.used_lrs, + hyp_vgic_nr_lr); + hyp_vcpu->vcpu.arch.pid = host_vcpu->arch.pid; } diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c index d461981616d9..ebc6b4afc336 100644 --- a/arch/arm64/kvm/hyp/nvhe/setup.c +++ b/arch/arm64/kvm/hyp/nvhe/setup.c @@ -20,6 +20,7 @@ #include unsigned long hyp_nr_cpus; +unsigned int hyp_vgic_nr_lr; #define hyp_percpu_size ((unsigned long)__per_cpu_end - \ (unsigned long)__per_cpu_start) > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. Best regards, Hyunwoo Kim