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[34.168.149.56]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85df0b315esm15840734a12.26.2026.06.08.13.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2026 13:51:04 -0700 (PDT) Date: Mon, 8 Jun 2026 20:51:00 +0000 From: David Matlack To: Pranjal Shrivastava Cc: kexec@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-pci@vger.kernel.org, Adithya Jayachandran , Alexander Graf , Alex Williamson , Bjorn Helgaas , Chris Li , David Rientjes , Jacob Pan , Jason Gunthorpe , Jonathan Corbet , Josh Hilke , Leon Romanovsky , Lukas Wunner , Mike Rapoport , Parav Pandit , Pasha Tatashin , Pratyush Yadav , Saeed Mahameed , Samiullah Khawaja , Shuah Khan , Vipin Sharma , William Tu , Yi Liu Subject: Re: [PATCH v6 01/12] PCI: liveupdate: Set up FLB handler for the PCI core Message-ID: References: <20260522202410.3104264-1-dmatlack@google.com> <20260522202410.3104264-2-dmatlack@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Rspam-User: X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: D91F2100005 X-Stat-Signature: yrffkksojqrsbnq9yo3ep39shcu11esm X-HE-Tag: 1780951867-673611 X-HE-Meta: U2FsdGVkX1/1ino3sznhAe8VDFe7ZxvYQY7zqWZKZhVWbTzjzrxl13AdOrWYx2LQfQeLalKNEc1h/EcINOFP2Un8pmtywHy4J+xF72jSulBDzViFHxuMOdFZ2pKxWvCcs/VYoF6oLjfvNIa5LyX8hvNzHO2HfYPcfdxfYlb2vb4QP14hNvgIwNax3tYln2zmnLEdfFoegWNiKh1DmB8P24/w5z7lalx+yuPbHKMDlfhqCgfh3RvdP7CYuMRnzwFGWMzns8g5smxdDkO/e7DNNYK2aUfOs8Rr0q4nJied4v2IUDTkkOsuyRD22JINsXHJF7BmR0/ysFLC8bZr9tyPJ55rKiXQyGOgr7LCgsNpTS69VuLqdf8x5Oa5/4+HnoSrNvTOx6oY74tqPbZSCujEatpeVQ94Y+lOn0ofTYMN/U9oRagqdilU97hlylKdIeZZVWcrnk4cvJ7yAGQVWVKv8ngTWZOd0B30OZyiWsMR2eOL/Z1Ty1bJx4y1fZh8lrpq0/6Fr9y7CiQT+zeOi5wI5g5U0QqpnCh0e133gqZKl9RmaLq45yzorLu0LSGUXRbfiCipTXpZi7kp2UNPPWzrfzQuV+18o/gvaiWQFvr/seOw4ptHZE0xRD1T9CYpwLo5XVkECHIwlGyIe7NpvrHZTtIC6zcjJe6pM39OskC3KKP0mV1ftrpN7chzBn/CNGwLBiXtD6ANkzE6pSOU78O0EYLuO/fhYHh2JEztjk4gNJa+f+8VWZfb6NcJwoed/fcGu71Mfmy4dobrHXIlBcyr32OIFYNJE+CSaaeEvH45CLSaBViBhAYrvjHYt5EylKK9l/CyufBDL/bBVxH6SBxJvxk6aE/958Sfve/RTdzgAQ8l2yGwejCMDsk86AxeanbWAcavzmq5tAlHns4iHfdtkXSFRK+6pQk4zlWShLyZDQPeUC2S2mJoWi17/3A4vHkepnVI8V2C3i6vsZyx0/q hXj9jAQc rSkUOhKqfxjVXH+Ns2F3OiYAdcfKq7QeGfr7R6H3q1FXoL/isRtnCXF4okz27PyoMyeP+3LqFWRbc8ZnME+SSz/M37Ie97Hk3xgo2paSBXbkCoQfE5rc7VfuWtCFP7NUpelMLgHIeTyg+0oDP/+dTPVSU9UCMpxxb2VoOG+8GeYTs1X15mzZyAwXloElUaFJlqTVfVWm2gziaBf3aGukMGA5rMQumf9mWU/EdLGFI8QzmbixYl/sMF5UxqGjpoiqP38RPjXuS3/NITnOrpSMtTFcFXG8OmRF8Xugg4DgN7ieYZmQ79U4WmSc8FsqkOvvmmBDIKamI3WL+MkI0GyCzFYPW9/2cCL/+pAPw Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On 2026-06-05 05:41 AM, Pranjal Shrivastava wrote: > On Fri, May 22, 2026 at 08:23:59PM +0000, David Matlack wrote: > > Set up a File-Lifecycle-Bound (FLB) handler for the PCI core to enable > > it to participate in the preservation of PCI devices across Live Update. > > Essentially, this commit enables the PCI core to allocate a struct > > (struct pci_ser) and preserve it across a Live Update whenever at least > > one device is preserved. > > > > Preserving PCI devices across Live Update is built on top of the Live > > Update Orchestrator's (LUO) support for file preservation. Drivers are > > expected to expose a file to userspace to represent a single PCI device > > and support preservation of that file. This is intended primarily to > > support preservation of PCI devices bound to VFIO drivers. > > > > This commit enables drivers to register their liveupdate_file_handler > > with the PCI core so that the PCI core can do its own tracking and > > enforcement of which devices are preserved. > > > > pci_liveupdate_register_flb(driver_file_handler); > > pci_liveupdate_unregister_flb(driver_file_handler); > > > > When the first file (with a handler registered with the PCI core) is > > preserved, the PCI core will be notified to allocate its tracking struct > > (pci_ser). When the last file is unpreserved (i.e. preservation > > cancelled) the PCI core will be notified to free struct pci_ser. > > > > This struct is preserved across a Live Update using KHO and can be > > fetched by the PCI core during early boot (e.g. during device > > enumeration) so that it knows which devices were preserved. > > > > Note: This commit only allocates struct pci_ser and preserves it across > > Live Update. A subsequent commit will add an API for drivers to tell the > > PCI core exactly which devices are being preserved. > > > > Note: There is no reason to check for kho_is_enabled() since it can be > > assumed to return true. If KHO was not enabled then Live Update would > > not be enabled and these routines would never run. > > > > [...] > > > +/** > > + * struct pci_dev_ser - Serialized state about a single PCI device. > > + * > > + * @domain: The device's PCI domain number (segment). > > + * @bdf: The device's PCI bus, device, and function number. > > + * @padding: Padding to naturally align struct pci_dev_ser. > > + */ > > +struct pci_dev_ser { > > + u32 domain; > > + u16 bdf; > > + u16 padding; > > +} __packed; > > + > > +/** > > + * struct pci_ser - PCI Subsystem Live Update State > > + * > > + * This struct tracks state about all devices that are being preserved across > > + * a Live Update for the next kernel. > > + * > > + * @max_nr_devices: The length of the devices[] flexible array. > > + * @nr_devices: The number of devices that were preserved. > > + * @devices: Flexible array of pci_dev_ser structs for each device. > > + */ > > +struct pci_ser { > > + u32 max_nr_devices; > > + u32 nr_devices; > > + struct pci_dev_ser devices[]; > > +} __packed; > > + > > +/* Ensure all elements of devices[] are naturally aligned. */ > > +static_assert(offsetof(struct pci_ser, devices) % sizeof(unsigned long) == 0); > > +static_assert(sizeof(struct pci_dev_ser) % sizeof(unsigned long) == 0); > > Minor Nit: Shall we consider using specific bitwidth types here? > I'm wondering if down the line another u32 field is added to > struct pci_dev_ser.. in that case on a 32-bit machine 12 % 4 == 0 but on > a 64-bit machine 12 % 8 != 0.. I think natural alignment is what matters for efficient access of the array elements. So failing the assert only on 64-bit architectures seems like the correct behavior. > > [...] > > With the nit: > > Reviewed-by: Pranjal Shrivastava > > Thanks, > Praan