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From: Jiri Wiesner <jwiesner@suse.de>
To: Dimitri Sivanich <sivanich@hpe.com>
Cc: "Thomas Gleixner" <tglx@linutronix.de>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	"Steve Wahl" <steve.wahl@hpe.com>,
	"Justin Ernst" <justin.ernst@hpe.com>,
	"Kyle Meyer" <kyle.meyer@hpe.com>,
	"Russ Anderson" <russ.anderson@hpe.com>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Borislav Petkov" <bp@alien8.de>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	"Peter Zijlstra (Intel)" <peterz@infradead.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Marco Elver" <elver@google.com>,
	"Guilherme G. Piccoli" <gpiccoli@igalia.com>,
	"Nikunj A Dadhania" <nikunj@amd.com>,
	"Xin Li (Intel)" <xin@zytor.com>,
	"Dimitri Sivanich" <dimitri.sivanich@hpe.com>
Subject: Re: [PATCH v4 0/2] x86/tsc: Exempt recent UV systems from clocksource watchdog checks to avoid false positives.
Date: Tue, 9 Jun 2026 11:59:26 +0200	[thread overview]
Message-ID: <aifj_l0St5tJ2BrN@incl> (raw)
In-Reply-To: <ag-6okJPQs7MMcis@hpe.com>

On Thu, May 21, 2026 at 09:08:34PM -0500, Dimitri Sivanich wrote:
> On Thu, May 21, 2026 at 09:30:14PM +0200, Thomas Gleixner wrote:
> > On Thu, May 21 2026 at 08:17, Dimitri Sivanich wrote:
> > > HPE UV hardware and firmware is designed to ensure a reliable and
> > > synchronized TSC mechanism.  Comparing the TSC against secondary
> > > clocksources can result in false positives due to variable access
> > > latency caused by system traffic.

I do not think that the access latency of the reference clocksource, sgi_rtc in this case, is the cause of the false positives. I think sgi_rtc really experiences time skew. More details below.

> The best course of action against
> > > these false positives has been found to simply disable watchdog
> > > checking of the TSC.
> > >
> > > Commits [1] and [2] were introduced to avoid an issue where the TSC
> > > is falsely declared unstable by exempting qualified platforms of up
> > > to 4-sockets from TSC clocksource watchdog checking.  Extend that
> > > exemption to include recent and future UV platforms.
> > 
> > Jiri asked you in the V3 submission:
> > 
> >  "A new implementation of the clocksource watchdog has been merged into
> >   the upstream kernel. One of the changes made by the new clocksource
> >   watchdog implementation is that reference clocksource reads are made
> >   on the boot CPU only. Perhaps, the sgi_rtc clocksource would work well
> >   with this implementation. So, testing is needed in order to find out
> >   if this patch are any future in the upstream Linux. Dimitri, would you
> >   be able to run tests on UV systems to check if the new clocksource
> >   watchdog implementation works and the hardware limitations of sgi_rtc
> >   do not get in the way?"
> > 
> > This question is still not answered by you and it has been confirmed
> > that the new watchdog works flawlessly on a 1920 threads 16 socket
> > system under massive load and system traffic.
> 
> I tested a 7.1-rc4 kernel on a 2048 thread 16 socket system and, while
> under test, the TSC did get marked as unstable after a series of "sgi_rtc
> read timed out" warnings.

The new clocksource watchdog implementation makes sure to act on time skew only if the time between two reference clocksource readouts does not exceed 50 us. The threshold for evaluating time skew (based on SHIFT_500PPM) is 244 us for a 500 ms interval plus the measured reference clocksource readout latency. If the comparison to the reference clocksource fails on CPU 0 the time skew between the clocksource being checked and the reference clocksource must be at least 244 us. The clocksource watchdog cannot distiguish which of the clocksources is skewed, and it must make the assumption that the clocksource being checked is skewed.

In the past, I worked on a bug where a customer with an HPE UV machine reported degraded performance and switches to the HPET. This kernel had the old clocksource watchdog implementation. I created a debugging kernel with the HPET as a second watchdog (not affecting the decisions by the watchdog) and got this result:
> clocksource: timekeeping watchdog on CPU118: Marking clocksource 'tsc' as unstable because the skew is too large:
> clocksource: 'sgi_rtc' wd_nsec: 511302794 wd_now: 1cb50e4c4b wd_last: 1ca7097111 mask: ffffffffffffff
> clocksource: 'hpet' wd2_nsec: 512005960 wd2_now: 65892719 wd2_last: 64c5d684 mask: ffffffff
> clocksource: 'tsc' cs_nsec: 512006458 cs_now: 86b5982cb1 cs_last: 867581bbab mask: ffffffffffffffff
> clocksource: 'tsc' skewed 703664 ns (0 ms) over watchdog 'sgi_rtc' interval of 511302794 ns (511 ms)
> clocksource: 'tsc' is current clocksource.
> tsc: Marking TSC unstable due to clocksource watchdog
> clocksource: Checking clocksource tsc synchronization from CPU 610 to CPUs 0-609,611-767.
> clocksource: Switched to clocksource sgi_rtc

The intervals measured by the TSC and the HPET match very well; the sgi_rtc is off. I find it hard to believe that both the TSC and the HPET would be skewed - both reporting a longer interval - while sgi_rtc was correct. I think sgi_rtc was skewed.

There are several solution to work around the hardware limitation of sgi_rtc:
1. Disable the clocksource watchdog
2. Decrease the rating of sgi_rtc
3. Disable sgi_rtc

Solution 3 in the form of a nouvrtc parameter was previously rejected on this mailing list. The disadvantage of the solution is that each customer would have to pass the nouvrtc parameter to the kernel to avoid false positives by the clocksource watchdog, which makes no sense from the POV of OS support (as done by e.g. SUSE).
-- 
Jiri Wiesner
SUSE Labs

  reply	other threads:[~2026-06-09  9:59 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-21 13:17 [PATCH v4 0/2] x86/tsc: Exempt recent UV systems from clocksource watchdog checks to avoid false positives Dimitri Sivanich
2026-05-21 13:20 ` [PATCH v4 1/2] x86/platform/uv: Expose the uv_hub_type() interface Dimitri Sivanich
2026-05-21 13:23 ` [PATCH v4 2/2] x86/tsc: Disable clocksource watchdog checking on recent and future UV platforms Dimitri Sivanich
2026-05-21 19:30 ` [PATCH v4 0/2] x86/tsc: Exempt recent UV systems from clocksource watchdog checks to avoid false positives Thomas Gleixner
2026-05-22  2:08   ` Dimitri Sivanich
2026-06-09  9:59     ` Jiri Wiesner [this message]
2026-06-09 19:34       ` Dimitri Sivanich

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