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[34.142.255.199]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-842828e21c8sm24873083b3a.49.2026.06.09.03.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 03:09:38 -0700 (PDT) Date: Tue, 9 Jun 2026 10:09:32 +0000 From: Pranjal Shrivastava To: Daniel Mentz Cc: iommu@lists.linux.dev, Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Nicolin Chen , Ashish Mhetre , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v8 09/12] iommu/arm-smmu-v3: Implement pm_runtime & system sleep ops Message-ID: References: <20260601215909.3958732-1-praan@google.com> <20260601215909.3958732-10-praan@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260609_030940_278564_C4D9656D X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Jun 07, 2026 at 03:30:00PM -0700, Daniel Mentz wrote: > On Mon, Jun 1, 2026 at 2:59 PM Pranjal Shrivastava wrote: > > +static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) > > +{ > > + struct arm_smmu_device *smmu = dev_get_drvdata(dev); > > + struct arm_smmu_cmdq *cmdq = &smmu->cmdq; > > + int timeout = ARM_SMMU_SUSPEND_TIMEOUT_US; > > + u32 enables, target; > > + int ret; > > + > > + /* Abort all transactions before disable to avoid spurious bypass */ > > + arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); > > + > > + /* Disable the SMMU via CR0.EN and all queues except CMDQ */ > > + enables = CR0_CMDQEN; > > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); > > + if (ret) { > > + dev_err(smmu->dev, "failed to disable SMMU\n"); > > + return ret; > > + } > > + > > + /* > > + * At this point the SMMU is completely disabled and won't access > > + * any translation/config structures, even speculative accesses > > + * aren't performed as per the IHI0070 spec (section 6.3.9.6). > > + */ > > + > > + /* Mark the CMDQ to stop and get the target index before the stop */ > > + target = atomic_fetch_or_relaxed(CMDQ_PROD_STOP_FLAG, &cmdq->q.llq.atomic.prod); > > I'm wondering if we need the non-relaxed version of atomic_fetch_or() > here to benefit from the barrier guarantees. Otherwise, how do you > ensure that CMDQ_PROD_STOP_FLAG isn't set before SMMUEN is cleared? Ack. I agree we need a non-relaxed version, I missed that the STOP_FLAG is purely RAM & was focused on the _relaxed variants to keep things ordered as all were MMIO. I'll drop the relaxed semantics with the STOP_FLAG. > > > + target &= CMDQ_PROD_IDX_MASK; Thanks, Praan