From: Chao Liu <chao.liu.zevorn@gmail.com>
To: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, philmd@oss.qualcomm.com,
pierrick.bouvier@oss.qualcomm.com,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 02/24] target/riscv: move TCG only files to tcg subdir
Date: Sat, 27 Jun 2026 19:04:44 +0800 [thread overview]
Message-ID: <aj-uQGobIWJ9PTam@ChaodeMacBook-Pro.local> (raw)
In-Reply-To: <20260622193141.1449724-3-daniel.barboza@oss.qualcomm.com>
On Mon, Jun 22, 2026 at 04:31:18PM +0800, Daniel Henrique Barboza wrote:
> We have *way* too much TCG-only code hanging around in target/riscv,
> where ideally we would have things that are shared between accelerators.
>
> We'll follow the example of other targets like i386 and loongarch and
> move everything to the tcg subir. This will not only cleanup target/riscv
> but it will also expose what is common code but it's buried inside a TCG
> helper.
>
> We're leaving some stuff behind because these require a little more
> case to not end up breaking KVM. We'll take care of them next.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> ---
> target/riscv/meson.build | 16 ----------
> target/riscv/{ => tcg}/bitmanip_helper.c | 0
> target/riscv/{ => tcg}/cpu_helper.c | 0
> target/riscv/{ => tcg}/crypto_helper.c | 0
> target/riscv/{ => tcg}/csr.c | 0
> target/riscv/{ => tcg}/debug.c | 0
> target/riscv/{ => tcg}/fpu_helper.c | 0
> .../insn_trans/trans_privileged.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rva.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
> .../insn_trans/trans_rvzicfiss.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
> .../insn_trans/trans_xventanacondops.c.inc | 0
> .../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
> target/riscv/{ => tcg}/m128_helper.c | 0
> target/riscv/tcg/meson.build | 30 +++++++++++++++++--
> target/riscv/{ => tcg}/mips_csr.c | 0
> target/riscv/{ => tcg}/op_helper.c | 0
> target/riscv/{ => tcg}/pmu.c | 0
> target/riscv/{ => tcg}/th_csr.c | 0
> target/riscv/{ => tcg}/translate.c | 0
> target/riscv/{ => tcg}/vcrypto_helper.c | 0
> target/riscv/{ => tcg}/vector_helper.c | 0
> target/riscv/{ => tcg}/vector_internals.c | 0
> target/riscv/{ => tcg}/vector_internals.h | 0
> target/riscv/{ => tcg}/zce_helper.c | 0
> 49 files changed, 28 insertions(+), 18 deletions(-)
> rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
> rename target/riscv/{ => tcg}/cpu_helper.c (100%)
> rename target/riscv/{ => tcg}/crypto_helper.c (100%)
> rename target/riscv/{ => tcg}/csr.c (100%)
> rename target/riscv/{ => tcg}/debug.c (100%)
> rename target/riscv/{ => tcg}/fpu_helper.c (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
> rename target/riscv/{ => tcg}/m128_helper.c (100%)
> rename target/riscv/{ => tcg}/mips_csr.c (100%)
> rename target/riscv/{ => tcg}/op_helper.c (100%)
> rename target/riscv/{ => tcg}/pmu.c (100%)
> rename target/riscv/{ => tcg}/th_csr.c (100%)
> rename target/riscv/{ => tcg}/translate.c (100%)
> rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.h (100%)
> rename target/riscv/{ => tcg}/zce_helper.c (100%)
>
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 79f36abd63..61874ed0af 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -16,31 +16,15 @@ riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
>
> riscv_ss.add(files(
> 'cpu.c',
> - 'cpu_helper.c',
> - 'csr.c',
> - 'fpu_helper.c',
> 'gdbstub.c',
> - 'op_helper.c',
> - 'vector_helper.c',
> - 'vector_internals.c',
> - 'bitmanip_helper.c',
> - 'translate.c',
> - 'm128_helper.c',
> - 'crypto_helper.c',
> - 'zce_helper.c',
> - 'vcrypto_helper.c'
> ))
>
> riscv_system_ss = ss.source_set()
> riscv_system_ss.add(files(
> 'arch_dump.c',
> 'pmp.c',
> - 'debug.c',
> 'monitor.c',
> 'machine.c',
> - 'mips_csr.c',
> - 'pmu.c',
> - 'th_csr.c',
> 'time_helper.c',
> 'riscv-qmp-cmds.c',
> ))
> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/tcg/bitmanip_helper.c
> similarity index 100%
> rename from target/riscv/bitmanip_helper.c
> rename to target/riscv/tcg/bitmanip_helper.c
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
> similarity index 100%
> rename from target/riscv/cpu_helper.c
> rename to target/riscv/tcg/cpu_helper.c
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/tcg/crypto_helper.c
> similarity index 100%
> rename from target/riscv/crypto_helper.c
> rename to target/riscv/tcg/crypto_helper.c
> diff --git a/target/riscv/csr.c b/target/riscv/tcg/csr.c
> similarity index 100%
> rename from target/riscv/csr.c
> rename to target/riscv/tcg/csr.c
> diff --git a/target/riscv/debug.c b/target/riscv/tcg/debug.c
> similarity index 100%
> rename from target/riscv/debug.c
> rename to target/riscv/tcg/debug.c
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/tcg/fpu_helper.c
> similarity index 100%
> rename from target/riscv/fpu_helper.c
> rename to target/riscv/tcg/fpu_helper.c
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/tcg/insn_trans/trans_privileged.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_privileged.c.inc
> rename to target/riscv/tcg/insn_trans/trans_privileged.c.inc
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/tcg/insn_trans/trans_rva.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rva.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rva.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/tcg/insn_trans/trans_rvb.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvb.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvb.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/tcg/insn_trans/trans_rvbf16.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvbf16.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvbf16.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/tcg/insn_trans/trans_rvd.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvd.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvd.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/tcg/insn_trans/trans_rvf.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvf.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvf.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/tcg/insn_trans/trans_rvh.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvh.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvh.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/tcg/insn_trans/trans_rvi.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvi.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvi.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/tcg/insn_trans/trans_rvk.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvk.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvk.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/tcg/insn_trans/trans_rvm.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvm.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvm.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvv.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvv.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/tcg/insn_trans/trans_rvvk.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvvk.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvvk.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/tcg/insn_trans/trans_rvzabha.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzabha.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzabha.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/tcg/insn_trans/trans_rvzacas.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzacas.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzacas.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzalasr.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzawrs.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/tcg/insn_trans/trans_rvzce.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzce.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzce.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzcmop.c.inc b/target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzcmop.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/tcg/insn_trans/trans_rvzfa.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzfa.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzfa.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzfh.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzicbo.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzicfiss.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicond.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzicond.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzicond.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzimop.c.inc b/target/riscv/tcg/insn_trans/trans_rvzimop.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzimop.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzimop.c.inc
> diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_svinval.c.inc
> rename to target/riscv/tcg/insn_trans/trans_svinval.c.inc
> diff --git a/target/riscv/insn_trans/trans_xlrbr.c.inc b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xlrbr.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xlrbr.c.inc
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/tcg/insn_trans/trans_xmips.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xmips.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xmips.c.inc
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xthead.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xthead.c.inc
> diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xventanacondops.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc
> diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/tcg/insn_trans/trans_zilsd.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_zilsd.c.inc
> rename to target/riscv/tcg/insn_trans/trans_zilsd.c.inc
> diff --git a/target/riscv/m128_helper.c b/target/riscv/tcg/m128_helper.c
> similarity index 100%
> rename from target/riscv/m128_helper.c
> rename to target/riscv/tcg/m128_helper.c
> diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
> index 061df3d74a..5684fcf985 100644
> --- a/target/riscv/tcg/meson.build
> +++ b/target/riscv/tcg/meson.build
> @@ -1,2 +1,28 @@
> -riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
> - 'tcg-cpu.c'))
> +if 'CONFIG_TCG' not in config_all_accel
> + subdir_done()
> +endif
> +
> +riscv_ss.add(files(
> + 'bitmanip_helper.c',
> + 'cpu_helper.c',
> + 'csr.c',
> + 'crypto_helper.c',
> + 'fpu_helper.c',
> + 'm128_helper.c',
> + 'op_helper.c',
> + 'translate.c',
> + 'tcg-cpu.c',
> + 'vcrypto_helper.c',
> + 'vector_helper.c',
> + 'vector_internals.c',
> + 'zce_helper.c'))
> +
> +
> +riscv_system_ss.add(files(
> + 'debug.c',
> + 'mips_csr.c',
> + 'pmu.c',
> + 'th_csr.c',
> +))
> +
> +
> diff --git a/target/riscv/mips_csr.c b/target/riscv/tcg/mips_csr.c
> similarity index 100%
> rename from target/riscv/mips_csr.c
> rename to target/riscv/tcg/mips_csr.c
> diff --git a/target/riscv/op_helper.c b/target/riscv/tcg/op_helper.c
> similarity index 100%
> rename from target/riscv/op_helper.c
> rename to target/riscv/tcg/op_helper.c
> diff --git a/target/riscv/pmu.c b/target/riscv/tcg/pmu.c
> similarity index 100%
> rename from target/riscv/pmu.c
> rename to target/riscv/tcg/pmu.c
> diff --git a/target/riscv/th_csr.c b/target/riscv/tcg/th_csr.c
> similarity index 100%
> rename from target/riscv/th_csr.c
> rename to target/riscv/tcg/th_csr.c
> diff --git a/target/riscv/translate.c b/target/riscv/tcg/translate.c
> similarity index 100%
> rename from target/riscv/translate.c
> rename to target/riscv/tcg/translate.c
> diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/tcg/vcrypto_helper.c
> similarity index 100%
> rename from target/riscv/vcrypto_helper.c
> rename to target/riscv/tcg/vcrypto_helper.c
> diff --git a/target/riscv/vector_helper.c b/target/riscv/tcg/vector_helper.c
> similarity index 100%
> rename from target/riscv/vector_helper.c
> rename to target/riscv/tcg/vector_helper.c
> diff --git a/target/riscv/vector_internals.c b/target/riscv/tcg/vector_internals.c
> similarity index 100%
> rename from target/riscv/vector_internals.c
> rename to target/riscv/tcg/vector_internals.c
> diff --git a/target/riscv/vector_internals.h b/target/riscv/tcg/vector_internals.h
> similarity index 100%
> rename from target/riscv/vector_internals.h
> rename to target/riscv/tcg/vector_internals.h
> diff --git a/target/riscv/zce_helper.c b/target/riscv/tcg/zce_helper.c
> similarity index 100%
> rename from target/riscv/zce_helper.c
> rename to target/riscv/tcg/zce_helper.c
> --
> 2.43.0
>
next prev parent reply other threads:[~2026-06-27 11:05 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 01/24] target/riscv: Remove unused tcg/tcg.h include Daniel Henrique Barboza
2026-06-27 11:03 ` Chao Liu
2026-06-22 19:31 ` [PATCH 02/24] target/riscv: move TCG only files to tcg subdir Daniel Henrique Barboza
2026-06-22 20:52 ` Philippe Mathieu-Daudé
2026-06-27 11:04 ` Chao Liu [this message]
2026-06-22 19:31 ` [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm Daniel Henrique Barboza
2026-06-22 21:25 ` Philippe Mathieu-Daudé
2026-06-23 10:25 ` Philippe Mathieu-Daudé
2026-06-23 14:59 ` Richard Henderson
2026-06-27 11:45 ` Chao Liu
2026-06-22 19:31 ` [PATCH 04/24] target/riscv: move pmp files to tcg subdir Daniel Henrique Barboza
2026-06-22 20:53 ` Philippe Mathieu-Daudé
2026-06-27 11:51 ` Chao Liu
2026-06-22 19:31 ` [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only Daniel Henrique Barboza
2026-06-22 21:30 ` Philippe Mathieu-Daudé
2026-06-23 15:02 ` Richard Henderson
2026-06-23 17:25 ` Daniel Henrique Barboza
2026-06-23 21:15 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 06/24] target/riscv: move pmu.h to tcg subdir Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 07/24] target/riscv: move debug.h " Daniel Henrique Barboza
2026-06-22 20:55 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 08/24] target/riscv: remove csr.h from kvm-cpu.c Daniel Henrique Barboza
2026-06-22 20:57 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 09/24] target/riscv: move csr.h to tcg subdir Daniel Henrique Barboza
2026-06-22 20:58 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 10/24] target/riscv: move custom_csrs logic to tcg-cpu.c Daniel Henrique Barboza
2026-06-22 21:02 ` Philippe Mathieu-Daudé
2026-06-23 19:19 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 11/24] target/riscv: move riscv_cpu_set_nmi() " Daniel Henrique Barboza
2026-06-22 21:04 ` Philippe Mathieu-Daudé
2026-06-23 19:59 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 12/24] target/riscv: move valid_vm_* satp arrays to cpu.c Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 13/24] target/riscv: move some irq helpers " Daniel Henrique Barboza
2026-06-22 21:07 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 14/24] target/riscv: move riscv_cpu_claim_interrupts " Daniel Henrique Barboza
2026-06-22 21:08 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 15/24] target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 16/24] target/riscv: gate riscv_cpu_update_mip with tcg_enabled() Daniel Henrique Barboza
2026-06-22 21:12 ` Philippe Mathieu-Daudé
2026-06-23 20:40 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 17/24] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold() Daniel Henrique Barboza
2026-06-22 21:13 ` Philippe Mathieu-Daudé
2026-06-24 11:19 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 18/24] hw/riscv/riscv_hart.c isolate tcg only bits Daniel Henrique Barboza
2026-06-22 21:15 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 19/24] target/riscv/gdbstub.c: isolate TCG only checks Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 20/24] target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint Daniel Henrique Barboza
2026-06-22 21:16 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 21/24] target/riscv/tcg: remove unused riscv_cpu_get_geilen() Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 22/24] target/riscv: move riscv_cpu_set_geilen() to riscv-imsic Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 23/24] target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic Daniel Henrique Barboza
2026-06-22 21:17 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 24/24] gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job Daniel Henrique Barboza
2026-06-22 20:52 ` [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Pierrick Bouvier
2026-06-22 21:04 ` Daniel Henrique Barboza
2026-06-22 21:23 ` Philippe Mathieu-Daudé
2026-06-22 21:34 ` Pierrick Bouvier
2026-06-23 8:17 ` Philippe Mathieu-Daudé
2026-06-23 9:48 ` Daniel Henrique Barboza
2026-06-23 9:58 ` Peter Maydell
2026-06-23 11:38 ` Daniel Henrique Barboza
2026-06-23 16:10 ` Pierrick Bouvier
2026-06-23 19:01 ` Daniel Henrique Barboza
2026-06-23 19:16 ` Pierrick Bouvier
2026-06-26 1:41 ` Alistair Francis
2026-06-26 15:28 ` Pierrick Bouvier
2026-06-27 3:31 ` Konstantin Ryabitsev
2026-06-27 7:00 ` Pierrick Bouvier
2026-06-26 1:37 ` Alistair Francis
2026-06-26 15:25 ` Pierrick Bouvier
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