From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D229C288530 for ; Fri, 26 Jun 2026 17:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782493729; cv=none; b=Mc0V2KQhBhJWxQF9zCPjJJdPQQTHI4K754f4iYfqbRhw6hss300cAVvtUcDU4TriOEXyh9yCpxoTi/wJLSPaSTYnryZ6svYYyMjgLDtTnjJvsIsv5ckVpR49+ZT6Pd3banC1Z1fWD5ZyaWNyJz3hsHUljr+vsD2R8MNdj4sEbTg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782493729; c=relaxed/simple; bh=rb1Nhqvs1XlSDSk5VERksIA63vzT0pBLcAGctl0TJvA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=S+qp57sxFOZPtYEivj5Io/LV6ZwFmUC1cIfj2JJLnfp/I8j2BIP7EBP0qooZvswz3cyxXzeUJDHo3L172Kq80Ep/Aj7pJlm2/NFa4GNiLtvKAN+xhihXYxi9galAYjcx79SnnoaSz1ui/F68qZAd7yEGl7Txuw/wb12jPn1y7bA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=dRh2fSM1; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="dRh2fSM1" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 257AB1F60; Fri, 26 Jun 2026 10:08:42 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 957343F632; Fri, 26 Jun 2026 10:08:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1782493726; bh=rb1Nhqvs1XlSDSk5VERksIA63vzT0pBLcAGctl0TJvA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=dRh2fSM1w0RA/f7DdFOM6oKxz6hXfVBie5ckL/3weQ87bIDN7SCNt2xMtuwm9FhYp kyMLvwMZUagoubp85JXpDj2yZoTL7f7cvdigJoPrLCQJ2DFBRgtY40muEvErE3Pb5S ICovpjmRGZsUs7qjCbZW+YhPjjeER+GYX8VXMaBM= Date: Fri, 26 Jun 2026 18:08:41 +0100 From: Catalin Marinas To: Kiryl Shutsemau Cc: Will Deacon , James Morse , Mark Rutland , Marc Zyngier , Doug Anderson , Petr Mladek , Thomas Gleixner , Andrew Morton , Baoquan He , Puranjay Mohan , Usama Arif , Breno Leitao , Julien Thierry , Lecopzer Chen , Sumit Garg , kernel-team@meta.com, kexec@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, "Kiryl Shutsemau (Meta)" Subject: Re: [PATCH v4 4/4] arm64: escalate smp_send_stop() to an SDEI NMI as a last resort Message-ID: References: <97a870d0670b7e1c2fb9f5142f6e36c594282017.1781709543.git.kas@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <97a870d0670b7e1c2fb9f5142f6e36c594282017.1781709543.git.kas@kernel.org> On Wed, Jun 17, 2026 at 08:20:05PM +0100, Kiryl Shutsemau wrote: > +void sdei_nmi_stop_cpus(const cpumask_t *mask) > +{ > + unsigned int cpu; > + > + WRITE_ONCE(sdei_nmi_stopping, true); > + > + /* > + * Publish the flag before signalling. The SMC is a context-sync > + * event, not a barrier, so WRITE_ONCE() alone could let the store be > + * observed after the event it triggers. The barrier is cumulative: a > + * target that sees the event is guaranteed to see the flag. > + */ > + smp_wmb(); > + > + for_each_cpu(cpu, mask) > + sdei_nmi_fire(cpu); > +} The smp_wmb() is not sufficient here. In the GIC IPI code we use a dsb(ishst). It should be similar here. I think TF-A does this already but it's unclear from the SDEI spec that it is mandated. -- Catalin