Re: [PATCH v2] arm64: tlbflush: Don't broadcast if mm was only active on local cpu

[Mark Rutland <mark.rutland@arm.com>]

On Mon, Jun 15, 2026 at 03:44:20PM +0100, Will Deacon wrote:
> On Mon, Jun 15, 2026 at 01:39:43PM +0100, Mark Rutland wrote:
> > On Sun, Jun 14, 2026 at 12:04:44PM +0100, Will Deacon wrote:
> > > On Sat, May 23, 2026 at 07:17:10PM +0530, Linu Cherian wrote:
> > 
> > > >  static inline void flush_tlb_mm(struct mm_struct *mm)
> > > >  {
> > > >  	unsigned long asid;
> > > > +	bool local;
> > > >  
> > > > -	dsb(ishst);
> > > > +	local = flush_tlb_user_pre(mm, TLBF_NONE);
> > > >  	asid = __TLBI_VADDR(0, ASID(mm));
> > > > -	__tlbi(aside1is, asid);
> > > > -	__tlbi_user(aside1is, asid);
> > > > -	__tlbi_sync_s1ish(mm);
> > > > +	if (local) {
> > > > +		__tlbi(aside1, asid);
> > > > +		__tlbi_user(aside1, asid);
> > > > +		dsb(nsh);
> > > > +	} else {
> > > > +		__tlbi(aside1is, asid);
> > > > +		__tlbi_user(aside1is, asid);
> > > > +		__tlbi_sync_s1ish(mm);
> > > > +	}
> > > > +	flush_tlb_user_post(local);
> > > 
> > > I think you've changed this since Ryan's original patch, but why are you
> > > only calling __tlbi_sync_s1ish() for the !local case? Doesn't that break
> > > the erratum workaround when running as a VM if the vCPU is migrated?
> > 
> > The errata mitigated by __tlbi_sync_s1ish() only affect broadcast
> > maintenance (the 'ish' in the name was intended to convey that). No
> > workaround is necessary for local TLB maintenance; aside from anything
> > else, when some PE executes the DSB to complete the maintenance, that
> > DSB alone is sufficient to complete memory accesses made by that PE.
> > 
> > If it would make things clearer, we could add a __tlbi_sync_s1nsh()
> > helper for the local case, which would boil down to a DSB NSH.
> 
> No, I don't think that's what I'm concerned about.

I *think* you're missing the shape of the errata; more on that below.

> > Regardless of the erratum, to correctly handle a vCPU being migrated
> > from pCPU-x to pCPU-y, we rely on:
> > 
> > * The host to set HCR_EL2.FB to ensure that TLB maintenance is
> >   broadcast to the ISH domain.
> > 
> > * The host to set HCR_EL2.BSU to ensure the DSB is upgrade to ISH such
> >   that any guest-issued DSB NSH will it can complete any TLB maintenance
> >   that was upgraded to ISH.
> > 
> > * The host to issue a DSB ISH on pCPU-x before the vCPU can run on
> >   pCPU-y, to complete any outstanding maintenance that was issued on
> >   pCPU-x. IIUC a DSB ISH on pCPU-y is not architecturally sufficient; it
> >   must be executed on the same CPU which issued the TLB maintenance.
> > 
> > ... but as above, all of that should be independent of any of the errata
> > that require the workaround.
> 
> Yes, I understand all of the above but the case I'm struggling with is
> where a vCPU runs on a system that needs the TLB invalidation to be
> performed twice. For non-broadcast invalidation (from the guest
> perspective), this patch will mean that it only performs the
> invalidation once. So if the vCPU migrates to another physical CPU, can
> that effectively undo the HCR_EL2.FB upgrade unless KVM issues TLB
> invalidation as well as a DSB on migration?
> 
> Maybe I'm missing something, as it looks like upstream already elides
> the call to __tlbi_sync_s1ish() for the NOBROADCAST case.

The key thing is that these errata only affect the completion of memory
accesses, and only those accesses made by other (physical) PEs.

A single TLBI will correctly remove the actual TLB entries, and
HCR_EL2.{FB,BSU} will still ensure that TLB entries are removed from the
TLBs of other PEs.

The errata only prevent completion of memory accesses made on other
(physical) PEs, and:

* For accesses made by the vCPU which is issuing the TLBI(s):

  - Regardless of the errata, the hypervisor has to ensure that when a
    vCPU is migrated from pCPU-x to pCPU-y, any prior CMOs or TLBIs are
    completed, which requires the host to execute a DSB ISH on pCPU-x
    before the vCPU can be run on pCPU-y.

    Maybe we have a latent bug here?

  - Within the context of the vCPU thread, a DSB {NSH,ISH,OSH} will
    complete all prior accesses made by the vCPU *regardless* of any TLB
    invalidation.

* For accesses made by *other* vCPUs, either:

  - Software in the VM intended to complete concurrency accesses made by
    other vCPUs. In which case, regardless of the errata, using a local
    TLBI alone is a software bug since that's not guaranteed to affect
    other PEs.

  - Software did not intend to complete accesses made by other vCPUs.
    In which case, it's fine that they may have uncompleted accesses.

... but maybe I'm still missing your concern?

Mark.