Re: [PATCH v3 5/8] KVM: VMX: Prioritize DR7.GD=1 #DB over CPL>0 #GP on Intel

[Sean Christopherson <seanjc@google.com>]

On Mon, Jun 15, 2026, Jim Mattson wrote:
> On Fri, Jun 12, 2026 at 4:03 PM Sean Christopherson <seanjc@google.com> wrote:
> > Note, neither Intel's SDM nor AMD's APM says anything about the relative
> > priority, hence the empirical testing.  Arguably Intel's description of
> > DR7.GD:
> >
> >   causes a debug exception to be generated prior to any MOV instruction
> >   that accesses a debug register.
> >
> > implies that DR7.GD has higher priority.  But that's a fairly weak argument
> > as the statement would still hold true if the #GP due to CPL>0 had higher
> > priority, as the #GP would prevent any access to a DR.
> >
> > Fixes: 3b88e41a4134 ("KVM: SVM: Add intercept check for accessing dr registers")
> > Signed-off-by: Sean Christopherson <seanjc@google.com>
> > ---
> >  arch/x86/kvm/emulate.c | 7 ++++++-
> >  arch/x86/kvm/vmx/vmx.c | 6 +++---
> >  2 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
> > index 127a21eeef66..b4dc57fe0bc9 100644
> > --- a/arch/x86/kvm/emulate.c
> > +++ b/arch/x86/kvm/emulate.c
> > @@ -3834,6 +3834,7 @@ static int check_cr_access(struct x86_emulate_ctxt *ctxt)
> >
> >  static int check_dr_read(struct x86_emulate_ctxt *ctxt)
> >  {
> > +       bool is_intel = ctxt->ops->guest_cpuid_is_intel_compatible(ctxt);
> 
> Hmmm...Have you tested VIA? 

Nope.  I'll loop in the Zhaoxin folks when I post the KVM-Unit-Test code to at
least see what Zhaoxin CPUs do.  Zhaoxin is taking over the Centaur CPUID leaves,
so unless someone happens to have access to a VIA CPU, that's probably the best
we can do.

> Or even Hygon? How compatible is "<vendor>_compatible"?

I'm confident Hygon matches AMD, given that Hygon inherited pretty much all of
the Zen errata.