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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Biju <biju.das.au@gmail.com>
Cc: Ulf Hansson <ulfh@kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v17 06/17] mmc: renesas_sdhi: Introduce renesas_sdhi_hw_info to abstract clock mask
Date: Wed, 17 Jun 2026 14:35:48 +0200	[thread overview]
Message-ID: <ajKUpOHCaufy42NH@shikoro> (raw)
In-Reply-To: <20260603065731.93243-7-biju.das.jz@bp.renesas.com>

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On Wed, Jun 03, 2026 at 07:57:06AM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> The RZ/G3L SoC has 11 divider bits and requires a different clock mask in
> renesas_sdhi_set_clock().
> 
> Add a new renesas_sdhi_hw_info struct to hold hardware-specific
> parameters, starting with clk_mask. This replaces the hardcoded constant
> in renesas_sdhi_set_clock() with a value sourced from the per-device
> hw_info, and widens the clk variable from u32 to u64 accordingly, as
> clk_mask for RZ/G3L exceeds 32 bits.
> 
> Wire hw_info through renesas_sdhi_of_data_with_quirks (internalDMAC path)
> and a new renesas_sdhi_of_data_with_info wrapper (sysDMAC path), and plumb
> it into renesas_sdhi_probe() so it is stored in the per-instance
> renesas_sdhi struct.
> 
> All existing users are assigned sdhi_hw_info_generic, preserving current
> behaviour. No functional change.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No change.
> ---
>  drivers/mmc/host/renesas_sdhi.h               | 12 ++++
>  drivers/mmc/host/renesas_sdhi_core.c          |  7 +-
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c | 16 ++++-
>  drivers/mmc/host/renesas_sdhi_sys_dmac.c      | 66 ++++++++++++++-----
>  4 files changed, 81 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
> index 09bf9b24a8c3..a7fc525b7218 100644
> --- a/drivers/mmc/host/renesas_sdhi.h
> +++ b/drivers/mmc/host/renesas_sdhi.h
> @@ -41,6 +41,15 @@ struct renesas_sdhi_of_data {
>  
>  #define SDHI_CALIB_TABLE_MAX 32
>  
> +struct renesas_sdhi_hw_info {
> +	u64 clk_mask;
> +};
> +
> +struct renesas_sdhi_of_data_with_info {
> +	const struct renesas_sdhi_of_data *of_data;
> +	const struct renesas_sdhi_hw_info *info;
> +};

? Why don't you put it in renesas_sdhi_of_data and tmio_mmc_data
instead?

You wouldn't even need to put the default value in all other of_data by
using:

In the 'if (of_data)' block of probe():

	mmc_data->clk_mask = of_data->clk_mask

and outside of this block:

	if (!mmc_data->clk_mask) mmc_data->clk_mask = <default>;

or something similar.

The main thing is that we don't need a hw_info struct IMO. It should be
already all there...

Same for everything which gets added later to hw_info.


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  reply	other threads:[~2026-06-17 12:35 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-03  6:57 [PATCH v17 00/17] Add Renesas RZ/G3L SD/eMMC support Biju
2026-06-03  6:57 ` [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Biju
2026-06-17 12:19   ` Wolfram Sang
2026-06-17 12:42     ` Biju Das
2026-06-03  6:57 ` [PATCH v17 02/17] clk: renesas: r9a08g046: Add clock and reset entries for SDHI Biju
2026-06-17 12:55   ` Geert Uytterhoeven
2026-06-03  6:57 ` [PATCH v17 03/17] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L Biju
2026-06-04  9:32   ` Geert Uytterhoeven
2026-06-04  9:39     ` Biju Das
2026-06-03  6:57 ` [PATCH v17 04/17] mmc: renesas_sdhi: Fix whitespace alignment in struct renesas_sdhi_of_data Biju
2026-06-17 12:21   ` Wolfram Sang
2026-06-17 13:06     ` Biju Das
2026-06-03  6:57 ` [PATCH v17 05/17] mmc: renesas_sdhi_internal_dmac: Fix whitespace alignment in struct initializer Biju
2026-06-17 12:21   ` Wolfram Sang
2026-06-17 13:08     ` Biju Das
2026-06-03  6:57 ` [PATCH v17 06/17] mmc: renesas_sdhi: Introduce renesas_sdhi_hw_info to abstract clock mask Biju
2026-06-17 12:35   ` Wolfram Sang [this message]
2026-06-03  6:57 ` [PATCH v17 07/17] mmc: renesas_sdhi: Add max_divider to renesas_sdhi_hw_info Biju
2026-06-03  6:57 ` [PATCH v17 08/17] mmc: renesas_sdhi: Add tuning_delay hw_info flag Biju
2026-06-17 12:40   ` Wolfram Sang
2026-06-17 13:39     ` Biju Das
2026-06-17 14:19       ` wsa+renesas
2026-06-03  6:57 ` [PATCH v17 09/17] mmc: renesas_sdhi: Add internal_divider hw_info flag for clk rate adjustment Biju
2026-06-03  6:57 ` [PATCH v17 10/17] mmc: renesas_sdhi: Add optional axis/axim reset controls Biju
2026-06-03  7:47   ` Philipp Zabel
2026-06-03  8:02     ` Biju Das
2026-06-03  6:57 ` [PATCH v17 11/17] mmc: renesas_sdhi: Add RZ/G3L SDHI support Biju
2026-06-17 12:51   ` Wolfram Sang
2026-06-03  6:57 ` [PATCH v17 12/17] mmc: renesas_sdhi: Save and restore IOVS across suspend/resume Biju
2026-06-03  6:57 ` [PATCH v17 13/17] mmc: renesas_sdhi: Add RZ/G3L HS400 support Biju
2026-06-03  6:57 ` [PATCH v17 14/17] mmc: renesas_sdhi: Add HS400 enhanced strobe support for RZ/G3L Biju
2026-06-12 12:47   ` Biju Das
2026-06-03  6:57 ` [PATCH v17 15/17] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK Biju
2026-06-03  6:57 ` [PATCH v17 16/17] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0 Biju
2026-06-03  6:57 ` [PATCH v17 17/17] arm64: dts: renesas: rzg3l-smarc-som: Enable SDHI2 Biju
2026-06-03  7:00 ` [PATCH v17 00/17] Add Renesas RZ/G3L SD/eMMC support Biju Das
2026-06-03  7:13   ` Geert Uytterhoeven
2026-06-03  7:20     ` Biju Das
2026-06-03  7:19   ` wsa+renesas
2026-06-03  7:27     ` Biju Das
2026-06-12 13:51       ` Biju Das
2026-06-12 14:56         ` wsa+renesas

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